ZL2102_14 Datasheet, PDF (1/58 Pages) Intersil Corporation – 6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation

DATASHEET
6A Digital Integrated Synchronous Step-Down DC/DC
Regulator with Auto Compensation
ZL2102
The ZL2102 is an integrated digital power regulator with auto
compensation and power management functions in a small
package, resulting in a flexible and integrated solution, which
can be configured using the PowerNavigator™ graphical user
interface. This synchronous buck converter operates from a
4.5V to 14V input supply and provides from 0.54V to 5.5V
output voltage at up to 6A.
The ZL2102 can be configured for most applications using only
hardware pin straps to adjust switching frequency, output
voltage, UVLO, soft-start ramp/delay settings, sequencing
options, and SMBus address. For more advanced
configurations, the ZL2102 supports over 70 PMBus
commands. Output voltage/current is factory calibrated.
Internal synchronous power MOSFETs enable the ZL2102 to
deliver continuous loads up to 6A with high efficiency. An
internal Schottky bootstrap diode reduces discrete component
count. The ZL2102 also supports phase spreading to reduce
system input capacitance.
The ZL2102 uses the SMBus™ with PMBus™ protocol for
communication with a host controller and the Intersil's
proprietary Digital-DC™ bus for interoperability between other
Intersil devices.
Features
• Integrated MOSFET switches
• 6A continuous output current
• Adjustable 0.54V to 5.5V output range
• 4.5V to 14V input range
• Up to 90% efficiency
• Auto compensation for fast transient response
• SMBus compliant serial interface
• Snapshot™ parametric capture
• Internal nonvolatile memory
• Small footprint QFN package (6mmx6mm)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
Related Literature
• AN2010 "Thermal and Layout Guidelines for Digital-DC™
Products"
• AN2035 "Compensation Using CompZL™"
• TB389 "PCB Land Pattern and Surface Mount Guidelines for
QFN Packages"
INTERFACE
HARDWARE
CONTROL
HARDWARE
CONFIG
DDC Bus
SMBus
DDC
V2P5
10µF
SCL
VRA
4.7µF
SDA ZL2102 VR
4.7µF
SALRT
PG
MGN
EN
SYNC
VSET
SA
VDDS
VDDP
BST
C_B
0.1µF
CIN
100µF
LOUT
2.2µH
SW
VSEN
PGND
COUT
200µF
V_IN
12V
VOUT
3.3V
6A
FC
SGND
CFG
SS
DGND
ePAD
FIGURE 1. TYPICAL APPLICATION DIAGRAM
November 20, 2014
FN8440.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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