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ZL2005P_14 Datasheet, PDF (1/41 Pages) Intersil Corporation – Digital-DC™ Controller with Drivers and POLA/DOSA Trim
NORTECROECMOMMEMNDENEDDZERLDE6PF1OL00ARCNEEMWENDTESPIAGRNDTSata Sheet
December 16, 2011
Digital-DC™ Controller with Drivers and POLA/DOSA Trim
ZL2005P
FN6849.3
Description
The ZL2005P is an innovative mixed-signal power
conversion and management IC that combines a com-
pact, efficient, synchronous DC-DC buck controller,
adaptive drivers and key power and thermal manage-
ment functions in one IC, providing flexibility and
scalability while decreasing board space requirements
and design complexity. Zilker Labs Digital-DC tech-
nology enables a unique blend of performance and
features not available in either traditional analog or
newer digital approaches, resolving the issues associ-
ated with providing multiple low-voltage power
domains on a single PCB.
The ZL2005P is designed to be configured either as a
standard ZL2005 or as POLA/DOSA compatible
device.
All operating features can be configured by simple
pin-strap selection, resistor selection or through the
on-board serial port. The PMBus™-compliant
ZL2005P uses the SMBus™ serial interface for com-
munication with other Digital-DC products or a host
controller.
Features Power Conversion
• Efficient synchronous buck controller
• 3 V to 14 V input range
• 0.54 V to 5.5 V output range (with margin)
• Optional output voltage setting with VADJ pin
• ± 1% output accuracy
• Internal 3 A drivers support >40 A power stage
• Fast load transient response
• Phase interleaving
• RoHS compliant (6 x 6 mm) QFN package
Power Management
• Digital soft start/stop
• Precision delay and ramp-up
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• I2C/SMBus communication
• Output overvoltage and overcurrent protection
• Internal non-voltatile memory (NVM)
• PMBus compliant
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
DLY FC ILIM
EN PG (0,1) (0,1) (0,1) CFG UVLO V25 VR VDD
SS (0,1)
VTRK
MGN
SYNC
VADJ
SCL
SDA
SALRT
LDO
POWER
MANAGEMENT
NON-
VOLATILE
MEMORY
I2C
DRIVER
PWM
CONTROLLER
MONITOR
ADC
CURRENT
SENSE
TEMP
SENSOR
BST
GH
SW
GL
ISENA
ISENB
SA (0,1)
XTEMP VSEN
PGND SGND DGND
Figure 1. Block Diagram
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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