X4C105 Datasheet, PDF (1/19 Pages) Intersil Corporation – CPU Supervisor with NOVRAM and Output Ports

®
Data Sheet
X4C105
4K, NOVRAM/EEPROM
March 18, 2005
FN8124.0
CPU Supervisor with NOVRAM and
Output Ports
FEATURES
• 4Kbit serial EEPROM
—400kHz serial interface speed
—16-byte page write mode
• One nibble NOVRAM
—120ns NOVRAM access speed
— AUTOSTORE
—Direct/bus access of NOVRAM bits
• Four output ports
• Operates at 3.3V ± 10%
• Low voltage reset when V_CC < 3V
—3% accurate thresholds available
—Output signal shows low voltage condition
—Activates NOVRAM AUTOSTORE
—Internal block on EEPROM operation
• Max EEPROM/NOVRAM nonvolatile write cycle:
5ms
• High reliability
—1,000,000 endurance cycles
—Guaranteed data retention: 100 years
• 20-lead TSSOP package
BLOCK DIAGRAM
WP
Write Control Logic
HV Generation
Timing and Control
SCL
SDA
S1
S2
Command
Decode
and
Control
Logic
EEPROM
Array
Y Decoder
Data Register
DESCRIPTION
The low voltage X4C105 combines several functions
into one device. The first is a 2-wire, 4Kbit serial
EEPROM memory with write protection. A Write Pro-
tect (WP) pin provides hardware protection for the
upper half of this memory against inadvertent writes.
A one nibble NOVRAM is provided and occupies a sin-
gle location. This allows access of 4-bits in a single
150ns cycle. This is useful for tracking system opera-
tion or process status. The NOVRAM memory is com-
pletely isolated from the serial memory section.
A low voltage detect circuit activates a RESET pin
when V_CC drops below 3V. This signal also blocks
new read or write operations and initiates a NOVRAM
AUTOSTORE. The AUTOSTORE operation is pow-
ered by an external capacitor to ensure that the value
in the NOVRAM is always maintained in the event of a
power failure.
The four NOVRAM bits also appear on four separate
output pins to allow continuous control of external cir-
cuitry, such as ASICs.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
EEPROM
Memory
Static RAM
Memory
4Kbits
Low Voltage Detect
Power-on Reset
Output
Buffers
and
Latches
I/O
Buffers
Control
Logic
and
Timing
Voltage
Monitor
Supply
O0
O1
O2
O3
D0
D1
D2
D3
CE
OE
WE
CAP
V_CC
V_SS
RESET
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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