P6049A Datasheet, PDF (1/1 Pages) Intersil Corporation – Plastic Packages for Integrated Circuits

Plastic Packages for Integrated Circuits
Small Outline Transistor Plastic Packages (SC70-6)
0.20 (0.008) M C
CL
b
e
VIEW C
6
5
4
CL
E1
CL
E
1
2
3
e1
C
D
CL
A ^A2
A1
SEATING
PLANE
-C-
0.10 (0.004) C
WITH
PLATING
c
b
b1
c1
BASE METAL
4X θ1
SEATING
PLANE
C
4X θ1
R1
R
L
α
L1
GAUGE PLANE
L2
P6.049A
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN
MAX
MIN
MAX NOTES
A
0.031 0.039 0.80
1.00
-
A1
0.001 0.004 0.025 0.10
-
A2
0.034 0.036 0.85
0.90
-
b
0.006 0.012 0.15
0.30
-
b1
0.006 0.010 0.15
0.25
-
c
0.004 0.008 0.10
0.20
6
c1
0.004 0.006 0.10
0.15
6
D
0.073 0.085 1.85
2.15
3
E
0.084 BSC
2.1 BSC
-
E1
0.045 0.053 1.15
1.35
3
e
0.0256 Ref
0.65 Ref
-
e1
0.0512 Ref
1.30 Ref
-
L
0.010 0.018 0.26
0.46
4
L1
0.016 Ref.
0.400 Ref.
-
L2
0.006 BSC
0.15 BSC
-
N
6
6
5
R
0.004
-
0.10
-
-
α
0°
8°
0°
8°
-
NOTES:
Rev. 0 7/05
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
VIEW C
1