KAD5512P-50_0910 Datasheet, PDF (1/30 Pages) Intersil Corporation – 12-Bit, 500MSPS A/D Converter

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Data Sheet
KAD5512P-50
October 9, 2009
FN6805.3
12-Bit, 500MSPS A/D Converter
General Description
The KAD5512P-50 is a low-power, high-performance, 12-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process. The KAD5512P-50 is part of a
pin-compatible portfolio of 10, 12 and 14-bit A/Ds with
sample rates ranging from 125MSPS to 500MSPS.
The device utilizes two time-interleaved 12-bit, 250MSPS
A/D cores to achieve the ultimate sample rate of 500MSPS.
A single 500MHz conversion clock is presented to the
converter, and all interleave clocking is managed internally.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two
converter cores. These adjustments allow the user to
minimize spurs associated with the interleaving process.
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P-50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified
over the full industrial temperature range (-40°C to +85°C).
Pin-Compatible Family
MODEL
KAD5514P-25
KAD5514P-21
KAD5514P-17
KAD5514P-12
KAD5512P-50
KAD5512P-25, KAD5512HP-25
KAD5512P-21, KAD5512HP-21
KAD5512P-17, KAD5512HP-17
KAD5512P-12, KAD5512HP-12
KAD5510P-50
RESOLUTION
14
14
14
14
12
12
12
12
12
10
SPEED
(MSPS)
250
210
170
125
500
250
210
170
125
500
Features
• Programmable Gain, Offset and Skew control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
• Selectable Clock Divider: ÷1 or ÷2
• Clock Phase Selection
• Nap and Sleep Modes
• Two’s Complement, Gray Code or Binary Data Format
• DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
• Pb-Free (RoHS Compliant)
Applications
• Radar and Satellite Antenna Array Processing
• Broadband Communications
• High-Performance Data Acquisition
Key Specifications
• SNR = 65.9dBFS for f_IN = 105MHz (-1dBFS)
• SFDR = 82.0dBc for f_IN = 105MHz (-1dBFS)
• Total Power Consumption = 432mW
CLKP
CLKN
VINP
VINN
VCM
CLOCK GENERATION
AND
INTERLEAVE CONTROL
CLKOUTP
CLKOUTN
SHA
SHA
12-BIT
250 MSPS
ADC
VREF
DIGITAL
ERROR
CORRECTION
12-BIT
250 MSPS
ADC
VREF
1.25V
+
–
SPI
CONTROL
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved
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