ISLA214P50_1103 Datasheet, PDF (1/37 Pages) Intersil Corporation – 14-Bit, 500MSPS ADC Programmable Built-in Test Patterns

14-Bit, 500MSPS ADC
ISLA214P50
The ISLA214P50 is a 14-bit, 500MSPS analog-to-digital converter
designed with Intersil’s proprietary FemtoCharge™ technology on
a standard CMOS process. The ISLA214P50 is part of a
pin-compatible portfolio of 12 to 16-bit A/Ds with maximum
sample rates ranging from 130MSPS to 500MSPS.
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single 500MHz
conversion clock is presented to the converter, and all interleave
clocking is managed internally. The proprietary Intersil Interleave
Engine (I2E) performs automatic correction of offset, gain, and
sample time mismatches between the unit ADCs to optimize
performance.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue offline and
continuous calibration commands as well as configure many
dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA214P50 is available in a 72 Ld QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
• SNR @ 500MSPS
= 72.7dBFS f_IN = 30MHz
= 70.6dBFS f_IN = 363MHz
• SFDR @ 500MSPS
= 84dBc f_IN = 30MHz
= 76dBc f_IN = 363MHz
• Total Power Consumption = 835mW @ 500MSPS
Features
• Automatic Fine Interleave Correction Calibration
• Single Supply 1.8V Operation
• Clock Duty Cycle Stabilizer
• 75fs Clock Jitter
• 700MHz Bandwidth
• Programmable Built-in Test Patterns
• Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
• Nap and Sleep Modes
- 200µs Sleep Wake-up Time
• Data Output Clock
• DDR LVDS-Compatible or LVCMOS Outputs
• User-accessible Digital Temperature Monitor
Applications
• Radar Array Processing
• Software Defined Radios
• Broadband Communications
• High-Performance Data Acquisition
• Communications Test Equipment
CLKP
CLKN
CLOCK
MANAGEMENT
CLKOUTP
CLKOUTN
VINP
VINN
VCM
SHA
14-BIT
250 MSPS
ADC
VREF
Gain, Offset
and Skew
Adjustments
DIGITAL
I2E
ERROR
CORRECTION
D[13:0]P
D[13:0]N
ORP
ORN
SHA
14-BIT
250 MSPS
ADC
VREF
+
–
SPI
CONTROL
Pin-Compatible Family
MODEL
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
RESOLUTION
16
16
16
14
14
14
14
12
12
12
12
SPEED
(MSPS)
250
200
130
500
250
200
130
500
250
200
130
March 15, 2011
1
FN7571.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
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