ISL6532 Datasheet, PDF (1/14 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems

®
Data Sheet
July 2004
ISL6532
FN9112.3
ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6532 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply V_DDQ with high current during
S0/S1 states and standby current during S3 state. During
Run mode, a fully integrated sink-source regulator generates
an accurate (V_DDQ/2) high current V_TT voltage without the
need for a negative supply. A buffered version of the V_DDQ/2
reference is provided as V_REF.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. Both the switching
regulator and integrated standby LDO provide a maximum
static regulation tolerance of ±2% over line, load, and
temperature ranges. The output is user-adjustable by means
of external resistors down to 0.8V.
Switching the memory core output between the PWM
regulator and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings V_DDQ into regulation in
a controlled manner when returning to S0/S1 state from
S4/S5 or mechanical off states. During S0 the PGOOD signal
indicates that all supplies are within spec and operational.
Each output is monitored for under and over-voltage events.
Current limiting is included on the V_TT and V_DDQ standby
regulators. Thermal shutdown is integrated.
Pinout
ISL6532 (QFN) TOP VIEW
20 19 18 17 16
5VSBY 1
GND 2
VTT 3
VTT 4
VDDQ 5
GND
21
15 NCH
14 PGOOD
13 GND
12 COMP
11 FB
6 7 8 9 10
Features
• Generates 2 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate V_DDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
• ACPI Compliant Sleep State Control
• Integrated V_REF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- Both Outputs: ±2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Over Current Protection and Under/Over-Voltage
Monitoring of Both Outputs
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
• Pb-free available
Applications
• _{Single and Dual Channel DDR Memory Power Systems in}
ACPI compliant PCs
• _{Graphics cards - GPU and memory supplies}
• ASIC power supplies
• Embedded processor and I/O supplies
• DSP supplies
Ordering Information
TEMP. RANGE
PART NUMBER
(^oC)
PACKAGE
ISL6532CR
0 to 70 20 Ld 6x6 QFN
ISL6532CRZ
(See Note)
0 to 70
20 Ld 6x6 QFN
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
PKG.
DWG. #
L20.6x6
L20.6x6
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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