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IH5043CPE Datasheet, PDF (1/7 Pages) Intersil Corporation – Dual SPDT CMOS Analog Switch
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Data SPOheSeStOIBBLSEOSLUEBHTSEI-T5PI0TR4UO3TDEUPCRTODUCMTarch 2000
IH5043
File Number 3130.3
Dual SPDT CMOS Analog Switch
[ /Title
(IH504
3)
/Sub-
ject
(Dual
SPDT
CMOS
Ana-
log
Switch
)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
semi-
con-
ductor,
Dual
SPDT
CMOS
Ana-
log
Switch
)
/Cre-
ator ()
/DOCI
NFO
pdf-
mark
[
The IH5043 analog switch uses an improved, high voltage
CMOS monolithic technology. These devices provide ease
of use and performance advantages not previously
available from solid state switches.
Key performance advantage is TTL compatibility and ultra
low power operation. The quiescent current requirement is
less than 1mA. Also, the IH5043 guarantees Break-Before-
Make switching, accomplished by extending the tON time
(300ns Typ), so that it exceeds tOFF time (200ns Typ). This
insures that an ON channel will be turned OFF before an
OFF channel can turn ON. The need for external logic
required to avoid channel to channel shorting during
switching is eliminated.
Part Number Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
IH5043CPE
IH5043CY
0 to 70
0 to 70
16 Ld PDIP
16 Ld SOIC
PKG.
NO.
E16.3
M16.15
Schematic Diagram
FUNCTIONAL DRIVER, TYPICAL DRIVER, GATE (1/2 AS SHOWN)
V+
Q3
5K
Q4
Q1
2K
Q9
S1
FLOATS
D1
GND
Q10
IN
VL
Q11
Q2
400Ω
1K
S3
FLOATS
D3
Q12
10K
Q7
Q6
Q8
Q5
400Ω
V-
Features
• See HI504X for Other Functions
• Dual SPDT
• Switches Greater than 20VP-P Signals with ±15V Supplies
• Quiescent Current Less than 1mA
• Break-Before-Make Switching tOFF 200ns, tON 300ns (Typ)
• TTL, DTL, CMOS, PMOS Compatible
Pinout
IH5043
(PDIP, SOIC)
TOP VIEW
D1 1
NC 2
D3 3
S3 4
S4 5
D4 6
NC 7
D2 8
16 S1
15 IN1
14 V-
13 GND
12 VL
11 V+
10 IN2
9 S2
Functional Diagram
S1 16
S3 4
VL
12
V+
11
1 D1
3 D3
IN1 15
IN2 10
S2 9
8 D2
S4 5
13
6 D4
14
GND
V-
SWITCH STATES SHOWN ARE FOR LOGIC “1” INPUT
LOGIC
0
1
TRUTH TABLE
SWITCH 1, 2
Off
On
SWITCH 3, 4
On
Off
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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