HSP50415EVAL1 Datasheet, PDF (1/5 Pages) Intersil Corporation – HSP50415EVAL1 Evaluation Kit

TM
Data Sheet
HSP50415EVAL1
April 2000
File Number 4859
HSP50415EVAL1 Evaluation Kit
The HSP50415EVAL1 is an evaluation kit for the HSP50415
wideband programmable modulator. The kit consists of an
evaluation Circuit Card Assembly (CCA) complete with the
HSP50415 device and additional circuitry to provide for
control via a computer parallel port. Windows based
demonstration software is provided for full user
programmability and control of all HSP50415 operational
modes. The evaluation board provides digital outputs which
are accessible through a standard logic analyzer header. It
also provides both single ended and differential analog
outputs via standard SMA connectors. Documentation
includes a user’s manual, full evaluation board schematics
and PCB layout materials. Special filter files, pattern files
and example configuration script files are included for quickly
configuring the board.
Features
• Evaluation CCA Complete With HSP50415 Wideband
Programmable Modulator
• Windows Based Demonstration Software
• Example Files For Common Modulation Techniques
Reference Documents
• HSP50415EVAL1 Demonstration Software in File
HSP50415.exe
• Example Configuration Files in *.js, filter files in *.coe, and
Pattern Files in *.pat
• HSP50415EVAL1 Schematics in File sch415bx.pdf
• HSP50415EVAL1 Layout in File fab415bx.pdf
• HSP50415EVAL1 Bill of Material in File bom415bx.pdf
The latest version for all reference materials and programs is
available via the Intersil internet website:
‘www.intersil.com/commlink/download/hsp50415eval1’.
Block Diagram
COMPUTER
PARALLEL
PORT
P1 25 PIN ‘D’
U2
LPT PORT CY37256V CPLD
U1
LVX161284
IEEE XCVR
CONTROL /3
J14 TEST
SOCKET
/17
U8
HC244
BUFFER
JTAG /6
P5 JTAG
HEADER
DATA /18
CONTROL /7
ADDRESS /20
DEBUG /16
/4 _{D3-D6 STATUS}
LEDs
STATUS /4
CONTROL /8
J15 TEST
SOCKET
U3
ALVCH16823
DATA REG
J13 TEST
SOCKET
U7
CY7C1327
SRAM
P2 DEBUG
HEADER
U5
OSC
J5
SMA
U4
HSP50415 WIDEBAND PROG. MOD.
FEMPT, FOVRFL, FFULL LOCKDET
CE, WR, RD, RESET, ADDR<2:0>, INTREQ
CDATA<7:0>
TXEN
ISTRB
DIN<15:0>
I OUT<13:0>
IOUTA
IOUTB
DATACLK
SYSCLK/2
2XSYSCLK
REFCLK
CLK
QOUTA
PLLRC ^QOUTB
U6
OSC
J4
SMA
LOOP
FILTER
EXTERNAL CLK
EXTERNAL CLK
P3 TEST
HEADER
J2
T1
SMA
I OUT
T2
J3
SMA
Q OUT
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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