HSP50215EVAL Datasheet, PDF (1/45 Pages) Intersil Corporation – DSP Modulator Evaluation Board

User’s Manual
HSP50215EVAL
January 1999 File Number 4463.3
DSP Modulator Evaluation Board
Evaluation Kit
The HSP50215EVAL Kit provides the necessary tools to
evaluate the HSP50215 Digital Upconverter integrated
circuit and consists of a circuit board and a software
program. The kit is designed for evaluation of Digital
Quadrature Amplitude, FM, and Shaped FM modulation for
IF Communications Applications. The circuit board uses
baseband I and Q data patterns loaded through the 8-bit
parallel interface or the ISAbus interface. Data is output as
either a digital or analog modulated composite IF signal. Up
to four channels can be included in the composite IF output.
To facilitate the use of the board during evaluation, the kit
includes example files for configuration, shaping filters and
input stimulus.
Circuit Board
The Functional Block Diagram illustrates the major functions
of the circuit board. The circuit board is a ISAbus form factor
with 40 pin I/O header/connectors for cascade and output
signals. Baseband test patterns are loaded through the
ISAbus or 8-bit parallel interface. The external Cascade
Input allows expansion of the number of channels in the
composite signal. The board outputs data through both the
RF connector and the 40 pin header. Test connectors are
provided at key signal and control locations in the circuit.
Features
• Multi-Channel Composite IF Output with 1-4 Channels
• Digital or Analog Composite Output
• Baseband Pattern Stimulus Files with Lengths to 64Kbits
• Example Baseband Patterns for BPSK, QPSK, π/4QPSK,
16QAM, FM, GMSK and AWG Noise
• Baseband Patterns Loaded to RAM Via PC ISAbus or
Parallel Port, for Use as Modulator Baseband Data
• DOS Based Configuration/Status Software
Applications
• Evaluation Tool for the Performance of the Digital
UpConverter Configured as PSK, Quadrature Amplitude
(QAM), FM and Shaped FM (MSK) Modulators at Rates
from <1 KBPS to 1.5 MBPS
• Performance Evaluation Tool for Digital Upconversion
• Communications Test Equipment
Functional Block Diagram
40 PIN
CONNECTOR
16
(CASCADE
INPUT)
HSP50215
DIGITAL
16
UPCONVERTER
CHANNEL 4
HSP50215
DIGITAL
16
UPCONVERTER
CHANNEL 3
HSP50215
DIGITAL
16
UPCONVERTER
CHANNEL 2
V_CC
FPGA
FPGA
FPGA
-12V
DATA
ADDRESS
RAM
RAM
RAM
INTERFACE BUS
(INPUT DATA PATH AND CONTROL/STATUS INTERFACE)
(OPTIONAL FINAL STAGE BASEBAND DATA INPUT PATH)
8
DATA
ADDRESS
WR
HSP50215
DIGITAL
UPCONVERTER
CHANNEL 1
40 PIN
CONNECTOR
16
14
FPGA
D/A
HI5741
RAM
8
DATA
ADDRESS
WR
V_CC
-12V
ADDRESS DECODE
OSC
INTERNAL
CLOCKS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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