HSP45256883 Datasheet, PDF (1/9 Pages) Intersil Corporation – Binary Correlator

TM
HSP45256/883
December 1999
Features
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Binary Correlator
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Reconfigurable 256 Stage Binary Correlator
• 1-Bit Reference x 1, 2, 4, or 8-Bit Data
• Separate Control and Reference Interfaces
• Configurable for 1-D and 2-D Operation
• Double Buffered Mask and Reference
• Programmable Output Delay
• Cascadable
• Standard Microprocessor Interface
Applications
The Intersil HSP45256/883 is a high-speed, 256 tap binary
correlator. It can be configured to perform one-dimensional
or two-dimensional correlations of selectable data precision
and length. Multiple HSP45256’s can be cascaded for
increased correlation length. Unused taps can be masked
out for reduced correlation length.
The correlation array consists of eight 32-tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8-bit input
data with a 1-bit reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
configured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The Mask Register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
• Radar/Sonar
• Spread Spectrum Communications
• Pattern/Character Recognition
• Error Correction Coding
Ordering Information
PART NUMBER
TEMP.
RANGE (^oC) PACKAGE
HSP45256GM-20/883 -55 to 125 85 Ld CPGA
HSP45256GM-25/883 -55 to 125 85 Ld CPGA
PKG.
NO.
G85.A
G85.A
The9- output of the correlation array (correlation score)
feeds the weight and sum logic, which gives added flexibility
to the data format. In addition, an offset register is provided
so that a preprogrammed value can be added to the correla-
tion score. This result is then passed through a user pro-
grammable delay stage to the cascade summer. The delay
stage simplifies the cascading of multiple correlators by
compensating for the latency of previous correlators.
The Binary Correlator is configured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the Control and Reference Registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
Block Diagram
DIN0-7
DREF0-7
256 TAP
CORRELATION
ARRAY
WEIGHT
AND SUM
MUX
DOUT0-7
AUXOUT0-8
DCONT0-7
A0-2
CASIN0-12
CONTROL
DELAY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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CASCADE
SUMMER
CASOUT0-12
FN2997.4