HSP45240_99 Datasheet, PDF (1/6 Pages) Intersil Corporation – Address Sequencer

TM
HSP45240/883
December 1999
Features
FOR
call
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Processing
Address Sequencer
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Block Oriented 24-Bit Sequencer
• Configurable as Two Independent 12-Bit Sequencers
• 24 x 24 Crosspoint Switch
• Programmable Delay on 12 Outputs 9-
• Multi-Chip Synchronization Signals
• Matrix Math Operations
Ordering Information
PART NUMBER
TEMP.
RANGE (^oC) PACKAGE
HSP45240GM-25/883 -55 to 125 68 Ld PGA
HSP45240GM-33/883 -55 to 125 68 Ld PGA
HSP45240GM-40/883 -55 to 125 68 Ld PGA
PKG.
NO.
• Standard µP Interface
• 100pF Drive on Outputs
• DC to 40MHz Clock Rate
Applications
• 1-D, 2-D Filtering
• Pan/Zoom Addressing
Description
The Intersil HSP45240/883 is a high speed Address
Sequencer which provides specialized addressing for func-
tions like FFTs, 1-D and 2-D filtering, matrix operations, and
image manipulation. The sequencer supports block oriented
addressing of large data sets up to 24 bits at clock speeds
up to 40MHz.
Block Diagram
STARTIN
START
CIRCUITRY
DLYBLK
SEQUENCE
GENERATOR
12
REG
24 _CROSS-POINT
SWITCH
12 _DELAY
1-8
PROCESSOR INTERFACE
D0-6, CS, A0, WR
STARTOUT
ADDVAL
DONE
BLOCKDONE
OUT12-23
OEH
OUT0-11
OEL
BUSY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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