HSP43881883 Datasheet, PDF (1/7 Pages) Intersil Corporation – Digital Filter

TM
Data Sheet
HSP43881/883
May 1999
FN2449.4
Digital Filter
The HSP43881/883 is a video speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of eight filter cells cascaded
internally and a shift and add output stage, all in a single
integrated circuit. Each filter cell contains a 8 x 8-bit
multiplier, three decimation registers and a 26-bit
accumulator. The output stage contains an additional 26-bit
accumulator which can add the contents of any filter cell
accumulator to the output stage accumulator shifted right by
8-bits. The HSP43881/883 has a maximum sample rate of
25.6MHz. The effective multiply accumulate (mac) rate is
204MHz.
The HSP43881/883 DF can be configured to process
expanded coefficient and word sizes. Multiple DFs can be
cascaded for larger filter lengths without degrading the
sample rate or a single DF can process larger filter lengths
at less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The DF provides for 8-bit unsigned or two’s complement
arithmetic, independently selectable for coefficients and
signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates
of ¹/₂, ¹/₃ or ¹/₄ the input sample rate. These registers also
provide the capability to perform 2-D operations such as
matrix multiplication and N x N spatial correlations/convolutions
for image processing applications.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 0MHz to 25.6MHz Sample Rate
• Eight Filter Cells
• 8-Bit Coefficients and Signal Data
• Low Power CMOS Operation
• I_CCSB 500µA Maximum
• I_CCOP 160mA Maximum at 20MHz
• 26-Bit Accumulator Per Stage
• Filter Lengths Up to 1032 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART NUMBER
TEMP.
RANGE (^oC) PACKAGE
HSP43881GM-25/883 -55 to 125 85 Ld PGA
PKG.
NO.
G85.A
Block Diagram
V_CC V_SS
DIN0 - DIN7 TCS
DIENB
CIENB 5
DCMO - 1
ERASE
8
TCCI
CIN0 - 7 ⁸
DF
FILTER 8
CELL 0
RESET _{5 5}
26
CLK
ADR0 - 2
3
8
8
DF
FILTER 8
CELL 1
26
8
DF
FILTER 8
CELL 2
26
8
DF
FILTER 8
CELL 3
26
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1, ADR2
2
2
26
OUTPUT
STAGE
26
SUM0 - 25
8
DF
FILTER 8
CELL 4
26
8
DF
FILTER 8
CELL 5
26
8
DF
FILTER 8
CELL 6
26
8
DF
FILTER 8
CELL 7
26
TCCO
COUT0 - 7
COENB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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