HSP43481883 Datasheet, PDF (1/2 Pages) Intersil Corporation – Digital Filter

August 1999
Features
TM
HSP43481/883
NOT ^{RECOMMESNeeDEHDSPF4O3R88N1EW DESIGNS}
Description
Digital Filter
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 0MHz to 25.6MHz Sample Rate
• Four Filter Cells
• 8-Bit Coefficients and Signal Data
• Low Power CMOS Operation
- I_CCSB = 500µA Maximum
- I_CCOP = 110µA Maximum at 20MHz
• 26-Bit Accumulator Per Stage
• Filter Lengths Up To 1032 Taps
• Expandable Coefficient Size, Data Size and Filter Length
• Decimation by 2, 3 or 4
Applications
• 1-D and 2-D FIR Filters
• Radar/Sonar
• Adaptive Filters
• Echo Cancellation
• Complex Multiply-Add
• Sample Rate Converters
Ordering Information
PART NUMBER
HSP43481GM-20/883
HSP43481GM-25/883
TEMPERA-
TURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
PACKAGE
68 Lead PGA
68 Lead PGA
The HSP43481/883 is a video-speed Digital Filter (DF)
designed to efficiently implement vector operations such as
FIR digital filters. It is comprised of four filter cells cascaded
internally and a shift-and- add output stage, all in a single
integrated circuit. Each filter cell contains an 8 x 8 multiplier,
three decimation registers and a 26-bit accumulator which
can add the contents of any filter cell accumulator to the out-
put stage accumulator shifted right by eight-bits. The
HSP43481/883 has a maximum sample rate of 25.6MHz.
The effective multiply-accumulate (MAC) rate is 102MHz.
The HSP43481/883 can be configured to process expanded
coefficient and word sizes. Multiple devices can be cas-
caded for larger filter lengths without degrading the sample
rate or a single device can process larger filter lengths at
less than 25.6MHz with multiple passes. The architecture
permits processing filter lengths of over 1000 taps with the
guarantee of no overflows. In practice, most filter coefficients
are less than 1.0, making even larger filter lengths possible.
The HSP43481/883 provides for unsigned or two’s comple-
ment arithmetic, independently selectable for coefficients
and signal data.
Each DF filter cell contains three resampling or decimation
registers which permit output sample rate reduction at rates of
1_/2, 1_{/3 or} 1_{/4 the input sample rate. These registers also pro-}
vide the capability to perform 2-D operations such as N x N
spatial correlations/convolutions for image processing appli-
cations.
Block Diagram
V_CC V_SS
DIN0 - DIN7 TCS
DIENB
CIENB 5
DCM0 - DCM1
ERASE
TCCI
CIN0 - CIN7 ⁸
8
FILTER
CELL 0
8
8
8
8
FILTER
CELL 1
8
FILTER
CELL 2
8
RESET _{4 4}
26
CLK
ADR0 - 1
2
26
26
MUX
RESET
CLK
SHADD
SENBL
SENBH
ADR0, ADR1
2
2
26
OUTPUT
STAGE
26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2001, All Rights Reserved
3-193
8
FILTER
CELL 3
8
26
TCCO
COUT0 - COUT 7
COENB
File Number 2450.4