HSP43168883 Datasheet, PDF (1/10 Pages) Intersil Corporation – Dual FIR Filter

TM
Data Sheet
HSP43168/883
May 1999
FN3177.3
Dual FIR Filter
The HSP43168/883 Dual FIR Filter consists of two
independent 8-tap FIR filters. Each filter supports
decimation from 1 to 16 and provides on-board storage for
32 sets of coefficients. The Block Diagram shows two FIR
cells each fed by a separate coefficient bank and one of two
separate inputs. The outputs of the FIR cells are either
summed or multiplexed by the MUX/Adder. The compute
power in the FIR Cells can be configured to provide
quadrature filtering, complex filtering, 2-D convolution, 1-
D/2-D correlations, and interpolating/decimating filters.
The FIR cells take advantage of symmetry in FIR
coefficients by pre-adding data samples prior to
multiplication. This allows an 8-tap FIR to be implemented
using only 4 multipliers per filter cell. These cells can be
configured as either a single 16-tap FIR filter or dual 8-tap
FIR filters. Asymmetric filtering is also supported.
Decimation of up to 16 is provided to boost the effective number
of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16 x 16.
The flexibility of the dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies
applications such as polyphase or adaptive filtering.
The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
configuration of the device is controlled through a standard
microprocessor interface.
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR
• 10-Bit Data and Coefficients
• On-Board Storage for 32 Programmable
Coefficient Sets
• Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or
10 x 20-Bit Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
• 33MHz, 25.6MHz Versions
Applications
• Quadrature, Complex Filtering
• Correlation
• Image Processing
• PolyPhase Filtering
• Adaptive Filtering
Ordering Information
PART NUMBER
HSP43168GM-25/883
HSP43168GM-33/883
TEMP.
RANGE (^oC) PACKAGE
PKG.
NO.
-55 to 125 84 Ld PGA G84.A
-55 to 125 84 Ld PGA G84.A
Block Diagram
CIN0 - 9
A0 - 8
WR
CSEL0 - 4
10
INA0 - 9
10
9
COEFFICIENT
BANK A
FIR CELL A
INB0 - 9/ ¹⁰
OUT0 - 8
MUX
9
OEL
OEH
MUX
COEFFICIENT
BANK B
FIR CELL B
MUX /
ADDER
19
CONTROL /
CONFIGURATION
OUT9 - 27
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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