HS-83C55RH Datasheet, PDF (1/12 Pages) Intersil Corporation – Radiation Hardened 16K Bit CMOS ROM

®
HS-83C55RH
Radiation Hardened
September 1997
Features
• Radiation Hardened
- Total Dose 1 x 10⁵
- Transient Upset >
- Latch-Up Free > 1
• 2048 Words x 8 Bits
x1ERRPO1xAI0M-D1C^10(2MS8RiOR)AASDD(S(Si_c)i/)_o1s/sn-8t⁽_8a^PN8co_-tO^r_IFNo^{tTsSOuTERaRrEnEETRNdCeHSEcDOISWLhDM-n6oRDiM5rc)6EaEw4SlNw7SIDGRwuEHNp.iDSnpotorerrtsCile.cPnotiCemnOr/oHMtasSutPc}_C^-Lt8_E^I3A₁^CN5T₁^{5ROHUT41L0TI6ONLEEPKADVDI5BE,BWCRiOtANZCFEI}₄^GMS₀^UEARO_VD^LA_D^{STDIIOPRN 3OM}
• Electrically Equivalent to Sandia SA3002
CE2 2
39 PB7
• Pin Compatible with Intel 8355
CLK 3
38 PB6
• Bus Compatible with HS-80C85RH
RESET ₄
37 PB5
• Single 5 Volt Power Supply
NC 5
36 PB4
• Low Standby Current 100µA Max
READY 6
35 PB3
• Low Operating Current 2mA/MHz
IO/M 7
34 PB2
• Completely Static Design
IOR 8
33 PB1
• Internal Address Latches
RD 9
32 PB0
• Two General Purpose 8-Bit I/O Ports
IOW 10
31 PA7
• Multiplexed Address and Data Bus
ALE ₁₁
30 PA6
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55^oC to +125^oC
Description
AD0 12
AD1 13
AD2 14
29 PA5
28 PA4
27 PA3
The HS-83C55RH is a radiation hardened ROM and I/O chip fabricated
using the Intersil radiation hardened Self-Aligned Junction Isolated
(SAJI) silicon gate technology. Latch-up free operation is achieved by
the use of epitaxial starting material to eliminate the parasitic SCR effect
seen in conventional bulk CMOS devices.
The HS-83C55RH is intended for use with the HS-80C85RH radiation
hardened microprocessor system.
AD3 ₁₅
AD4 16
AD5 17
AD6 18
AD7 19
GND ₂₀
26 PA2
25 PA1
24 PA0
23 A10
22 A9
21 A8
The ROM portion is designed as 16,384 mask programmable cells orga-
nized in a 2048 word x 8-bit format. A maximum post irradiation access
time of 340ns allows the HS-83C55RH to be used with the HS-80C85RH
CPU without any wait states. This ROM is designed for operation utilizing
a single 5 volt power supply.
Block Diagram
CLK
READY
AD0-7
A8-10
CE2
CE1
IO/M
ALE
RD
IOW
RESET
IOR
2K X 8
ROM
PORT A
A
(8) PA0-7
PORT B
B
(8) _PB0-7
VDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright © Intersil Americas Inc. 2002. All Rights Reserved
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File Number 3045.2