HS-82C55ARH_00 Datasheet, PDF (1/17 Pages) Intersil Corporation – Radiation Hardened CMOS Programmable Peripheral Interface

TM
Data Sheet
HS-82C55ARH
August 2000 File Number 3191.2
Radiation Hardened CMOS Programmable
Peripheral Interface
The Intersil HS-82C55ARH is a high performance, radiation
hardened CMOS version of the industry standard 8255A and
is manufactured using a hardened field, self-aligned silicon
gate CMOS process. It is a general purpose programmable
I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized
into two 8-bit and two 4-bit ports. Each port may be
programmed to function as either an input or an output.
Additionally, one of the 8-bit ports may be programmed for
bidirectional operation, and the two 4-bit ports can be
programmed to provide handshaking capabilities. The high
performance, radiation hardness, and industry standard
configuration of the HS-82C55ARH make it compatible with
the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus
hold circuitry eliminates the need for pull-up resistors. The
Intersil hardened field CMOS process results in performance
equal to or greater than existing radiation resistant products
at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95819. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
5962R9581901QQC HS1-82C55ARH-8
5962R9581901VQC HS1-82C55ARH-Q
TEMP. RANGE
(^oC)
-55 to 125
-55 to 125
Features
• Electrically Screened to SMD # 5962-95819
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . . <10⁸ rad(Si)/s
- Latch Up Free EPI-CMOS
• Low Power Consumption
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µA
• Pin Compatible with NMOS 8255A and the Intersil 82C55A
• High Speed, No “Wait State” Operation with 5MHz
HS-80C86RH
• 24 Programmable I/O Pins
• Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up
Resistors
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• Hardened Field, Self-Aligned, Junction Isolated CMOS
Process
• Single 5V Supply
• 2.0mA Drive Capability on All I/O Port Outputs
• Military Temperature Range . . . . . . . . . . . -55^oC to 125^oC
Pinout
CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
PA3 1
PA2 2
PA1 3
PA0 4
RD 5
CS 6
GND 7
A1 8
A0 9
PC7 10
PC6 11
PC5 12
PC4 13
PC0 14
PC1 15
PC2 16
PC3 17
PB0 18
PB1 19
PB2 20
40 PA4
39 PA5
38 PA6
37 PA7
36 WR
35 RESET
34 D0
33 D1
32 D2
31 D3
30 D4
29 D5
28 D6
27 D7
26 VDD
25 PB7
24 PB6
23 PB5
22 PB4
21 PB3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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