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HS-81C55RH_00 Datasheet, PDF (1/11 Pages) Intersil Corporation – Radiation Hardened 256 x 8 CMOS RAM | |||
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TM
Data Sheet
HS-81C55RH, HS-81C56RH
August 2000 File Number 3039.2
Radiation Hardened 256 x 8 CMOS RAM
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
Speciï¬cations for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Speciï¬cations for these devices are
contained in SMD 5962-96766. A âhot-linkâ is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL
MKT. NUMBER
5962R9676601QXC HS1-81C55RH-8
5962R9676601QYC HS9-81C55RH-8
5962R9676601VXC
HS1-81C55RH-Q
5962R9676601VYC
HS9-81C55RH-Q
5962R9676602QXC HS1-81C56RH-8
5962R9676602QYC HS9-81C56RH-8
5962R9676602VXC
HS1-81C56RH-Q
5962R9676602VYC
HS9-81C56RH-Q
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Features
⢠Electrically Screened to SMD # 5962-96766
⢠QML Qualiï¬ed per MIL-PRF-38535 Requirements
⢠Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . .>1 x 108 rad(Si)/s
- Latch-Up Free . . . . . . . . . . . . . . . . . . >1 x 1012 rad(Si)/s
⢠Electrically Equivalent to Sandia SA 3001
⢠Pin Compatible with Intel 8155/56
⢠Bus Compatible with HS-80C85RH
⢠Single 5V Power Supply
⢠Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max
⢠Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz
⢠Completely Static Design
⢠Internal Address Latches
⢠Two Programmable 8-Bit I/O Ports
⢠One Programmable 6-Bit I/O Port
⢠Programmable 14-Bit Binary Counter/Timer
⢠Multiplexed Address and Data Bus
⢠Self Aligned Junction Isolated (SAJI) Process
⢠Military Temperature Range . . . . . . . . . . . -55oC to 125oC
Functional Diagram
IO/M
AD0 - AD7
CE OR CEâ
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
256 x 8
STATIC
RAM
PORT A
A
8 PA0 - PA7
PORT B
B
8 PB0 - PB7
C
TIMER
â 81C55RH = CE
81C56RH = CE
PORT C
8 PC0 - PC5
VDD (10V)
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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