HS-65647RH_00 Datasheet, PDF (1/8 Pages) Intersil Corporation – Radiation Hardened 8K x 8 SOS CMOS Static RAM

TM
Data Sheet
HS-65647RH
August 2000 File Number 2928.3
Radiation Hardened 8K x 8 SOS CMOS
Static RAM
The Intersil HS-65647RH is a fully asynchronous 8K x 8
radiation hardened static RAM. This RAM is fabricated using
the Intersil 1.2 micron silicon-on-sapphire CMOS technology.
This technology gives exceptional hardness to all types of
radiation, including neutron fluence, total ionizing dose, high
intensity ionizing dose rates, and cosmic rays.
Low power operation is provided by a fully static design. Low
standby power can be achieved without pull-up resistors,
due to the gated input buffer design.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95823. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
ORDERING NUMBER
INTERNAL MKT.
NUMBER
5962F9582301QXC HS1-65647RH-8
5962F9582301QYC HS-965647RH-8
5962F9582301VXC HS1-65647RH-Q
5962F9582301VYC HS9-65647RH-Q
HS1-65647RH/PROTO HS1-65647RH/PROTO
HS9-65647RH/PROTO HS9-65647RH/PROTO
TEMP.
RANGE (^oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
E1
E2
X
0
1
1
0
1
0
1
0
1
TRUTH TABLE
G
W
MODE
X
X Low Power Standby
X
X Disabled
1
1 Enabled
0
1 Read
X
0 Write
Features
• Electrically Screened to SMD # 5962-95823
• QML Qualified per MIL-PRF-38535 Requirements
• 1.2 Micron Radiation Hardened SOS CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . >1 x 10¹¹ rad(Si)/s
- Single Event Upset . . . . . . . . < 1 x 10^-12 Errors/Bit-Day
• Latch-up Free
• LET Threshold . . . . . . . . . . . . . . . . . . >250 MEV/mg/cm2
• Low Standby Supply Current . . . . . . . . . . . . . 10mA (Max)
• Low Operating Supply Current . . . . . . . . . .100mA (2MHz)
• Fast Access Time . . . . . . . . . . . . . 50ns (Max), 35ns (Typ)
• High Output Drive Capability
• Gated Input Buffers (Gated by E2)
• Six Transistor Memory Cell
• Fully Static Design
• Asynchronous Operation
• CMOS Inputs
• 5V Single Power Supply
• Military Temperature Range . . . . . . . . . . . -55^oC to 125^oC
• Industry Standard JEDEC Pinout
Functional Diagram
AI
ROW
ROW
DECODER
128 X 512
MEMORY ARRAY
I/O0
INPUT
COLUMN I/O
DATA
CIRCUIT _{COLUMN DECODER}
I/O7
AI COL
E2
E1
G
CONTROL
CIRCUIT
W
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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