HS-3182_07 Datasheet, PDF (1/7 Pages) Intersil Corporation – ARINC 429 Bus Interface Line Driver

®
Data Sheet
June 5, 2007
HS-3182
FN2963.2
ARINC 429 Bus Interface Line Driver
Circuit
The HS-3182 is a monolithic dielectrically isolated bipolar
differential line driver designed to meet the specifications of
ARINC 429. This Device is intended to be used with a
companion chip, HS-3282 CMOS ARINC Bus Interface
Circuit, which provides the data formatting and processor
interface function.
All logic inputs are TTL and CMOS compatible. In addition to
the DATA (A) and DATA (B) inputs, there are also inputs for
CLOCK and SYNC signals which are AND’d with the DATA
inputs. This feature enhances system performance and
allows the HS-3182 to be used with devices other than the
HS-3182.
Three power supplies are necessary to operate the HS-3182:
+V = +15V ±10%, -V = -15V ±10%, and V1 = 5V ±5%. V_REF is
used to program the differential output voltage swing such that
V_OUT (DIFF) = ±2VREF. Typically, V_REF = V1 = 5V ±5%, but a
separate power supply may be used for VREF which should
not exceed 6V.
The driver output impedance is 75Ω ±20% at +25°C. Driver
output rise and fall times are independently programmed
through the use of two external capacitors connected to the CA
and CB inputs. Typical capacitor values are CA = CB = 75pF for
high-speed operation (100kBPS), and CA = CB = 300pF for
low-speed operation (12kBPS to 14.5kBPS). The outputs are
protected against overvoltage and short circuit as shown in the
Block Diagram. The HS-3182 is designed to operate over an
ambient temperature range of -55°C to +125°C, or -40°C to
+85°C.
TABLE 1. TRUTH TABLE
SYNC CLK DATA (A) DATA (B) A_OUT B_OUT COMMENTS
XL
X
X
0V 0V
Null
LX
X
X
0V 0V
Null
HH
L
L
0V 0V
Null
HH
L
HH
H
HH
H
H
-V_REF +V_REF
L
+V_REF -V_REF
H
0V 0V
Low
High
Null
Features
• RoHS/Pb-free Available for SBDIP Package (100% Gold
Termination Finish)
• TTL and CMOS Compatible Inputs
• Adjustable Rise and Fall Times via Two External
Capacitors
• Programmable Output Differential Voltage via VREF Input
• Operates at Data Rates Up to 100k Bits/s
• Output Short Circuit Proof and Contains Overvoltage
Protection
• Outputs are Inhibited (0V) If DATA (A) and DATA (B)
Inputs are Both in the “Logic One” State
• DATA (A) and DATA (B) Signals are “AND’d” with Clock
and Sync Signals
• Full Military Temperature Range
Pinouts
HS-3182
(16 LD SBDIP)
TOP VIEW
V_REF 1
GND 2
SYNC 3
DATA (A) 4
C_A 5
A_OUT 6
-V 7
GND 8
16 V₁
15 NC
14 CLK
13 DATA (B)
12 C_B
11 B_OUT
10 NC
9 +V
HS-3182
(28 LD CLCC)
TOP VIEW
4 3 2 1 28 27 26
NC 5
25 CLK
DATA (A) 6
24 NC
NC 7
23 DATA (B)
NC 8
22 CB
CA 9
21 NC
NC 10
20 NC
NC 11
19 NC
12 13 14 15 16 17 18
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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