English
Language : 

HS-26CLV32RH Datasheet, PDF (1/3 Pages) Intersil Corporation – Radiation Hardened 3.3V Quad Differential Line Receiver
®
Data Sheet
HS-26CLV32RH
May 28, 2009
FN4907.2
Radiation Hardened 3.3V Quad Differential
Line Receiver
The Intersil HS-26CLV32RH is a radiation hardened 3.3V
quad differential line receiver designed for digital data
transmission over balanced lines, in low voltage, RS-422
protocol applications. Radiation hardened CMOS processing
assures low power consumption, high speed, and reliable
operation in the most severe radiation environments.
The HS-26CLV32RH has an input sensitivity of 200mV (Typ)
over a common mode input voltage range of -4V to +7V. The
receivers are also equipped with input fail safe circuitry,
which causes the outputs to go to a logic “1” when the inputs
are open. The device has unique inputs that remain high
impedance when the receiver is disabled or powered-down,
maintaining signal integrity in multi-receiver applications.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95689. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/military/
Features
• Electrically Screened to SMD # 5962-95689
• QML Qualified per MIL-PRF-38535 Requirements
• 1.2 Micron Radiation Hardened CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(Max)
- Single Event Upset LET . . . . . . . . . . . 100MeV/mg/cm2)
- Single Event Latch-up Immune
• Low Stand-by Current . . . . . . . . . . . . . . . . . . .13mA(Max)
• Operating Supply Range . . . . . . . . . . . . . . . . 3.0V to 3.6V
• Enable Input Levels . . .VIH > (0.7)(VDD); VIL < (0.3)(VDD)
• CMOS Output Levels . . . . . . . . VOH > 2.55V; VOL < 0.4V
• Input Fail Safe Circuitry
• High Impedance Inputs when Disabled or Powered-down
• Full -55°C to +125°C Military Temperature Range
• Pb-Free (RoHS Compliant)
Applications
• Line Receiver for MIL-STD-1553 Serial Data Bus
Logic Diagram
ENABLE ENABLE DIN DIN
CIN CIN
BIN BIN AIN AIN
+-
+-
+-
+-
DOUT
COUT
BOUT
AOUT
Ordering Information
ORDERING NUMBER
(Note)
INTERNAL MKT. NO.
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
5962F9568902QEC
HS1-26CLV32RH-8
Q 5962F95 68902QEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9568902QXC
HS9-26CLV32RH-8
Q 5962F95 68902QXC
-55 to +125
16 Ld FLATPACK K16.A
5962F9568902VEC
HS1-26CLV32RH-Q
Q 5962F95 68902VEC
-55 to +125
16 Ld SBDIP
D16.3
5962F9568902VXC
HS9-26CLV32RH-Q
Q 5962F95 68902VXC
-55 to +125
16 Ld FLATPACK K16.A
HS1-26CLV32RH/PROTO HS1-26CLV32RH/PROTO HS1- 26CLV32RH /PROTO
-55 to +125
16 Ld SBDIP
D16.3
HS9-26CLV32RH/PROTO HS9-26CLV32RH/PROTO HS9- 26CLV32RH /PROTO
-55 to +125
16 Ld FLATPACK K16.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2008, 2009.All Rights Reserved
All other trademarks mentioned are the property of their respective owners.