HM-6551_03 Datasheet, PDF (1/10 Pages) Intersil Corporation – 256 x 4 CMOS RAM

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Data Sheet
HM-6551/883
July 2003
FN2988.2
256 x 4 CMOS RAM
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
TEMP.
PACKAGE RANGE
220ns
300ns
PKG.
DWG. #
CERDIP
-55°C to HM1-6551B/883 HM1-6551/883 F22.4
+125°C
Pin Descriptions
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
S
Chip Select
D
Data Input
Q
Data Output
Features
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation. . . . . . . . . . . . . . . .20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
GND 8
D0 9
Q0 10
D1 11
22 VCC
21 A4
20 W
19 S1
18 E
17 S2
16 Q3
15 D3
14 Q2
13 D2
12 Q1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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