HM-65262883 Datasheet, PDF (1/10 Pages) Intersil Corporation – 16K x 1 Asynchronous CMOS Static RAM

TM
HM-65262/883
March 1997
16K x 1 Asynchronous
CMOS Static RAM
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55^oC to +125^oC
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
• Equal Cycle and Access Time
• Single 5V Supply
Description
The HM-65262/883 is a CMOS 16384 x 1-bit Static Ran-
dom Access Memory manufactured using the Intersil
Advanced SAJI V process. The device utilizes asynchro-
nous circuit design for fast cycle times and ease of use.
The HM-65262/883 is available in both JEDEC Standard
20 pin, 0.300 inch wide CERDIP and 20 pad CLCC pack-
ages, providing high board-level packing density. Gated
inputs lower standby current, and also eliminate the need
for pull-up or pull-down resistors.
The HM-65262/883, a full CMOS RAM, utilizes an array of
six transistor (6T) memory cells for the most stable and
lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of
the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of
four transistor (4T) devices.
Ordering Information
70ns/20µA
-
HM4-65262B/883
85ns/20µA
HM1-65262/883
HM4-65262/883
85ns/400µA
-
-
TEMP. RANGE
-55^oC to +125^oC
-55^oC to +125^oC
PACKAGE
CERDIP
CLCC
PKG. NO.
F20.3
J20.C
Pinouts
HM1-65262/883 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 7
Q8
W9
GND 10
20 VCC
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
12 D
11 E
A2 3
A3 4
A4 ₅
A5 ₆
A6 ₇
Q8
2 1 20 19
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
9 10 11 12
A0 - A13
Address Input
E
Chip Enable/Power Down
Q
Data Out
D
Data In
VSS/GND Ground
VCC Power (+5)
W
Write Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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