HM-6518 Datasheet, PDF (1/9 Pages) Intersil Corporation – 1024 x 1 CMOS RAM

HM-6518/883
March 1997
1024 x 1 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• High Noise Immunity
• On-Chip Address Register
• Two-Chip Selects for Easy Array Expansion
• Three-State Output
The HM-6518/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6518/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE
CERDIP
TEMP. RANGE
-55^oC to +125^oC
PART
NUMBER
HM1-6518/883
PKG. NO.
F18.3
Pinout
HM-6518/883
(CERDIP)
TOP VIEW
S1 1
E2
A0 3
A1 4
A2 5
A3 6
A4 7
Q8
GND 9
18 VCC
17 S2
16 D
15 W
14 A9
13 A8
12 A7
11 A6
10 A5
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
S
Chip Select
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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File Number 2986.1