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HM-6516883 Datasheet, PDF (1/8 Pages) Intersil Corporation – 2K x 8 CMOS RAM
TM
HM-6516/883
March 1997
2K x 8 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
The HM-6516/883 is a CMOS 2048 x 8 Static Random
Access Memory. Extremely low power operation is achieved
by the use of complementary MOS design techniques. This
low power is further enhanced by the use of synchronous cir-
cuit techniques that keep the active (operating) power low,
which also gives fast access times. The pinout of the HM-
6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard
which allows easy memory board layouts, flexible enough to
accommodate a variety of PROMs, RAMS, EPROMs, and
ROMs.
The HM-6516/883 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B/883
HM4-6516B/883
200ns
HM1-6516/883
-
TEMPERATURE RANGE PACKAGE PKG. NO.
-55oC to 125oC
CERDIP F24.6
-55oC to +125oC
CLCC
J32.A
Pinouts
HM-6516/883
(CERDIP)
TOP VIEW
HM-6516/883
(CLCC)
TOP VIEW
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN
DESCRIPTION
NC
No Connect
A0 - A10 Address Inputs
E
Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC Power (+5V)
W
Write Enable
G
Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FN2999.1