HM-6514883 Datasheet, PDF (1/9 Pages) Intersil Corporation – 1024 x 4 CMOS RAM

TM
HM-6514/883
March 1997
1024 x 4 CMOS RAM
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
• On-Chip Address Register
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-
cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.
On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
HM1-6514S/883
200ns
HM1-6514B/883
300ns
HM1-6514/883
TEMPERATURE RANGE PACKAGE
-55^oC to 125^oC
CERDIP
PKG. NO.
F18.3
Pinout
HM-6514/883
(CERDIP)
TOP VIEW
A6 1
A5 2
A4 3
A3 4
A0 5
A1 6
A2 7
E8
GND 9
18 VCC
17 A7
16 A8
15 A9
14 DQ0
13 DQ1
12 DQ2
11 DQ3
10 W
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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