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HM-6508 Datasheet, PDF (1/9 Pages) Intersil Corporation – 1024 x 1 CMOS RAM | |||
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HM-6508/883
March 1997
1024 x 1 CMOS RAM
Features
Description
⢠This Circuit is Processed in Accordance to
MIL-STD-883 and is Fully Conformant Under the Provi-
sions of Paragraph 1.2.1.
⢠Low Power Standby . . . . . . . . . . . . . . . . . . . . 50µW Max
⢠Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
⢠Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
⢠Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min
⢠TTL Compatible Input/Output
⢠High Output Drive - 2 TTL Loads
⢠On-Chip Address Register
The HM-6508/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address allowing efï¬cient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6508/883 is a fully static RAM and may be main-
tained in any state for an indeï¬nite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Ordering Information
PACKAGE TEMP. RANGE 180ns 250ns
CERDIP -55oC to +125oC HM1-
HM1-
6508B/883 6508/883
PKG. NO.
F16.3
Pinout
HM1-6508/883
(CERDIP)
TOP VIEW
E1
A0 2
A1 3
A2 4
A3 5
A4 6
Q7
GND 8
16 VCC
15 D
14 W
13 A9
12 A8
11 A7
10 A6
9 A5
PIN
DESCRIPTION
A
Address Input
E
Chip Enable
W
Write Enable
D
Data Input
Q
Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-69
File Number 2985.1
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