HIP7020 Datasheet, PDF (1/11 Pages) Intersil Corporation – J1850 Bus Transceiver For Multiplex Wiring Systems

HIP7020
June 1998
J1850 Bus Transceiver
For Multiplex Wiring Systems
Features
Description
• J1850 Bus Transceiver for MX Wiring
• 5V CMOS/TTL Logic Interface
• Current Controlled Transmitter Driver
• Controlled Rise/Fall Time of Bus Drive for Both
Voltage and Current
• Bus Drive Capability to Less Than 500Ω with a 5µs
Load RC Time Constant
• Filtered Bus Input Receiver
• Ground Fault Tolerant for Bus Isolation
• Short Circuit and Over Temperature Protection
• Protection for Reverse Battery, Load Dump
and Latch-Up
• ±9kV ESD Protection BUS OUT and BATTERY Pins
• -40^oC to 125^oC Operating Range
• Loop-Back Fault Detection Mode
• 4x (41.6kHz) Receive Speed
Ordering Information
PART
NUMBER
HIP7020AB
HIP7020AP
TEMP.
RANGE (^oC)
PACKAGE PKG. NO.
-40 to 125 8 Ld SOIC
M8.15
-40 to 125 8 Ld PDIP
E8.3
The HIP7020 IC is an Integrated I/O Bus Transceiver
designed for the SAE Standard J1850 Class B Data Com-
munication Network Interface. The Bus transmits and
receives data on a single wire using a 10.4kHz VPWM (Vari-
able Pulse Width Modulated) signal. The HIP7020 serves as
an I/O buffer interfacing to 5V CMOS logic. It is designed to
operate directly from the 12V battery line of an automobile.
The normal Bus voltage swing capability is from 0V to 7.75V
at currents greater than 20mA.
As shown in the Block Diagram, the Transmitter TX Input and
the Receiver RX Output of the Bus Transceiver Circuit inter-
face to the control logic. The TX input signal is wave shaped
for rise time, fall time and amplitude before it is converted
from voltage to current. The Wave Shaper with an external
programming resistor, R_S controls the rise and fall time of
the BUS OUT output signal. The current source drive to the
Bus is voltage controlled by the Wave Shaped Voltage Refer-
ence to a maximum limit as specified for the J1850 Bus and
includes short-circuit current limiting.
The HIP7020 Receiver input, BUS IN is connected to the
J1850 Bus through an external resistor, R_F and has a trip
point at one-half of the nominal Bus signal voltage which is
3.875V. The Receiver input is filtered to remove high fre-
quency Bus noise by the external resistor and an internal
capacitor. The Receiver Bus signal, after processing, is out-
put at the RX pin by the RX Buffer’s open collector driver.
The RX output is active low and requires an external pull-up
resistor returned to the control logic V_CC supply. This pre-
vents power-up of the control logic by the transceiver if V_CC
supply voltage is removed.
The HIP7020 has a Loop-Back Enable Mode Switch to
return diagnostic information for the Bus Transceiver node.
For an active low or an open LB EN input, the Trans-
mit/Receive signals are internally “Looped-Back” to provide
a TX to RX return signal path independent of signals on the
Bus. A return path validation indicates proper action of the
Bus Transceiver apart from the J1850 Bus.
Pinout
HIP7020
(PDIP, SOIC)
TOP VIEW
BATT 1
TX 2
R/F TIME 3
RX 4
8 GND
7 BUS OUT
6 LB EN
5 BUS IN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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File Number 3642.3