HIP6503_05 Datasheet, PDF (1/14 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

®
Data Sheet
July 21, 2005
HIP6503
FN4882.5
Multiple Linear Power Controller with
ACPI Control Interface
The HIP6503 complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20 pin SOIC package. One linear controller
generates the 3.3V_DUAL/3.3V_SB voltage plane from the ATX
supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. A linear controllers/regulator
supplies at choice either of 2.5V or 3.3V memory power
through external pass transistors (switch for 3.3V setting) in
active states. During sleep states, integrated pass
transistors supply the sleep power. Another controller
powers up the 5V_DUAL plane by switching in the ATX 5V
output in active states, and the ATX 5VSB in sleep states.
Two internal regulators output both a dedicated, noise-free
2.5V clock chip supply, as well as a 1.8V ICH2 resume well
voltage. The HIP6503’s operating mode (active outputs or
sleep outputs) is selectable through two digital control pins,
S3 and S5. Enabling sleep state support on the 5V_DUAL
output is offered through the EN5VDL pin. In active state, the
3.3V_DUAL/3.3V_SB and 2.5V_MEM/3.3V_MEM linear regulators
use external N-channel pass MOSFETs to connect the
outputs directly to the 3.3V input supplied by an ATX power
supply, for minimal losses. In sleep state, power delivery on
both outputs is transferred to NPN transistors. Active state
regulation on the 2.5V_MEM output is performed through an
external NPN transistor. The 5V_DUAL output is powered
through two external MOS transistors. In sleep states, a
PMOS (or PNP) transistor conducts the current from the ATX
5VSB output; while in active state, current flow is transferred
to an NMOS transistor connected to the ATX 5V output. The
operation of the 5V_DUAL output is dictated not only by the
status of the S3 and S5 pins, but that of the EN5VDL pin as
well. The 3.3V_DUAL/3.3V_SB and 1.8V_SB outputs are active
for as long as the ATX 5VSB voltage is applied to the chip.
The 2.5V_CLK output is only active during S0 and S1/S2, and
uses the 3V3 pin as input source for its internal pass
element.
Features
• Provides 5 ACPI-Controlled Voltages
- 5V_DUAL USB/Keyboard/Mouse
- 3.3V_DUAL/3.3V_SB PCI/Auxiliary/LAN
- 2.5V_MEM RDRAM or 3.3V_MEM SDRAM
- 2.5V_CLK Clock/Processor Terminations
- 1.8V_SB ICH2 Resume Well
• Excellent Output Voltage Regulation
- All Outputs: ±2.0% Over Temperature (as applicable)
• Small Size; Very Low External Component Count
• RDRAM/SDRAM/DDRAM Memory Support
• Undervoltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• _{ACPI-Compliant Power Regulation for Motherboards}
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
PKG.
DWG. #
HIP6503CB
0 to 70 20 Ld SOIC
M20.3
HIP6503CBZ (Note)
0 to 70 20 Ld SOIC (Pb-free) M20.3
HIP6503CBZ-T (Note) 20 Ld SOIC Tape and Reel
(Pb-free)
M20.3
HIP6503EVAL1
Evaluation Board
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
HIP6503
(SOIC)
TOP VIEW
5VSB 1
1V8IN 2
1V8SB 3
3V3DLSB 4
3V3DL 5
VCLK 6
3V3 7
EN5VDL 8
S3 ⁹
S5 ¹⁰
20 VSEN2
19 DRV2
18 5V
17 12V
16 SS
15 5VDL
14 5VDLSB
13 DLA
12 FAULT/MSEL
11 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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