HIP6501A_04 Datasheet, PDF (1/14 Pages) Intersil Corporation – Triple Linear Power Controller with ACPI Control Interface

®
Data Sheet
December 30, 2004
HIP6501A
FN4749.6
Triple Linear Power Controller with ACPI
Control Interface
The HIP6501A, paired with either the HIP6020 or HIP6021,
simplifies the implementation of ACPI-compliant designs in
microprocessor and computer applications. The IC
integrates two linear controllers and a low-current pass
transistor, as well as the monitoring and control functions
into a 16-pin SOIC package. One linear controller generates
the 3.3V_DUAL voltage plane from an ATX power supply’s
5VSB output during sleep states (S3, S4/S5), powering the
PCI slots through an external pass transistor, as instructed
by the status of the 3.3V_DUAL enable pin. An additional pass
transistor is used to switch in the ATX 3.3V output for PCI
operation during S0 and S1 (active) operatingstates. The
second linear controller supplies the computer system’s
2.5V/3.3V memory power through an external pass
transistor in active states. During S3 state, an integrated
pass transistor supplies the 2.5V/3.3V sleep-state power. A
third controller powers up a 5V_DUAL plane by switching in
the ATX 5V output in active states, or the ATX 5VSB in sleep
states.
The HIP6501A’s operating mode (active-state outputs or
sleep-state outputs) is selectable through two control pins:
S3 and S5. Further control of the logic governing activation
of different power modes is offered through two enabling
pins: EN3VDL and EN5VDL. In active states, the 3.3V_DUAL
linear regulator uses an external N-Channel pass MOSFET
to connect the output (V_OUT1) directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, while
incurring minimal losses. In sleep state, the 3.3V_DUAL output
is supplied from the ATX 5VSB through an NPN transistor,
also external to the controller. Active state power delivery for
the 2.5/3.3V_MEM output is done through an external NPN
transistor, or an NMOS switch for the 3.3V setting. In sleep
states, conduction on this output is transferred to an internal
pass transistor. The 5V_DUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output,
while in active states, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. Similar to the
3.3V_DUAL output, the operation of the 5V_DUAL output is
dictated not only by the status of the S3 and S5 pins, but that
of the EN5VDL pin as well.
Features
• Provides 3 ACPI-Controlled Voltages
- 5V Active/Sleep (5V_DUAL)
- 3.3V Active/Sleep (3.3V_DUAL)
- 2.5V/3.3V Active/Sleep (2.5V_MEM)
• Simple Control Design - No Compensation Required
• Excellent Output Voltage Regulation
- 3.3V_DUAL Output: ±2.0% Over Temperature; Sleep
States Only
- 2.5V/3.3V Output: ±2.0% Over Temperature; Both
Operational States (3.3V setting in sleep only)
• Fixed Output Voltages Require No Precision External
Resistors
• Small Size
- Small External Component Count
• Selectable 2.5V_MEM Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting
• Adjustable Soft-Start Function Eliminates 5VSB
Perturbations
• Pb-Free Available (RoHS Compliant)
Pinout
HIP6501A (SOIC)
TOP VIEW
5VSB 1
EN3VDL 2
3V3DLSB 3
3V3DL 4
EN5VDL 5
S3 6
S5 7
GND 8
16 VSEN2
15 DRV2
14 12V
13 SS
12 5VDL
11 5VDLSB
10 DLA
9 FAULT/MSEL
Ordering Information
TEMP.
PART NUMBER RANGE (°C)
PACKAGE
HIP6501ACB
0 to 70 16 Ld SOIC
HIP6501ACBZ
(Note)
0 to 70
16 Ld SOIC
(Pb-free)
HIP6501AEVAL1 Evaluation Board
*Add “-T” suffix to part number for tape and reel packaging.
PKG.
DWG. #
M16.15
M16.15
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
are RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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