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| HIP4020 Datasheet, PDF (1/8 Pages) Intersil Corporation – Half Amp Full Bridge Power Driver for Small 3V, 5V and 12V DC Motors | |||
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HIP4020
June 1997
Half Amp Full Bridge Power Driver
for Small 3V, 5V and 12V DC Motors
Features
Description
⢠Two Independent Controlled Complementary
MOS Power Output Half H-Drivers (Full-Bridge)
for Nominal 3V to 12V Power Supply Operation
⢠Split ±Voltage Power Supply Option for Output
Drivers
⢠Load Switching Capabilities to 0.5A
⢠Single Supply Range +2.5V to +15V
⢠Low Standby Current
⢠CMOS/TTL Compatible Input Logic
⢠Over-Temperature Shutdown Protection
⢠Over-Current Limit Protection
⢠Over-Current Fault Flag Output
⢠Direction, Braking and PWM Control
Applications
⢠DC Motor Driver
⢠Relay and Solenoid Drivers
⢠Stepper Motor Controller
⢠Air Core Gauge Instrument Driver
⢠Speedometer Displays
⢠Tachometer Displays
⢠Remote Power Switch
⢠Battery Operated Switch Circuits
⢠Logic and Microcontroller Operated Switch
In the Functional Block Diagram of the HIP4020, the four switches
and a load are arranged in an H-Conï¬guration so that the drive volt-
age from terminals OUTA and OUTB can be cross-switched to
change the direction of current ï¬ow in the load. This is commonly
known as 4-quadrant load control. As shown in the Block Diagram,
switches Q1 and Q4 are conducting or in an ON state when current
ï¬ows from VDD through Q1 to the load, and then through Q4 to termi-
nal VSSB; where load terminal OUTA is at a positive potential with
respect to OUTB. Switches Q1 and Q4 are operated synchronously
by the control logic. The control logic switches Q3 and Q2 to an open
or OFF state when Q1 and Q4 are switched ON. To reverse the cur-
rent ï¬ow in the load, the switch states are reversed where Q1 and Q4
are OFF while Q2 and Q3 are ON. Consequently, current then ï¬ows
from VDD through Q3, through the load, and through Q2 to terminal
VSSA, and load terminal OUTB is then at a positive potential with
respect to OUTA.
Terminals ENA and ENB are ENABLE Inputs for the Logic A and B
Input Controls. The ILF output is an Over-Current Limit Fault Flag Out-
put and indicates a fault condition for either Output A or B or both. The
VDD and VSS are the Power Supply reference terminals for the A and
B Control Logic Inputs and ILF Output. While the VDD positive power
supply terminal is internally connected to each bridge driver, the VSSA
and VSSB Power Supply terminals are separate and independent from
VSS and may be more negative than the VSS ground reference termi-
nal. The use of level shifters in the gate drive circuitry to the NMOS
(low-side) output stages allows controlled level shifting of the output
drive relative to ground.
Ordering Information
PART NUMBER
HIP4020IB
TEMP.
RANGE (oC)
-40 to 85
PACKAGE
20 Ld SOIC
PKG. NO.
M20.3
Pinout
HIP4020 SOIC
TOP VIEW
NC 1
ILF 2
B2 3
ENB 4
B1 5
VSS 6
ENA 7
A1 8
A2 9
NC 10
20 NC
19 VDD
18 NC
17 OUTB
16 VSSB
15 VSSA
14 OUTA
13 NC
12 VDD
11 NC
Block Diagram
VDD
B1
B2
ENB
A1
A2
ENA
ILF
ISENSE
Q1
ISENSE
Q3
OUTB
Q2
ISENSE
TSENSE
OUTA
Q4
ISENSE
VSS
VSSA
VSSB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3976.1
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