HCTS86MS Datasheet, PDF (1/9 Pages) Intersil Corporation – Radiation Hardened Quad 2-Input Exclusive OR Gate

HCTS86MS
October 1995
Radiation Hardened
Quad 2-Input Exclusive OR Gate
Features
Pinouts
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS86MS is a Radiation Hardened Quad 2-Input
Exclusive OR Gate. A high on any one input exclusively will
change the output to a High state.
The HCTS86MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS86MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
B4
A4
Y4
B3
A3
Y3
Functional Diagram
An
(1, 4, 9, 12)
Bn
(2, 5, 10, 13)
Yn
(3, 6, 8, 11)
PART
NUMBER
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
HCTS86DMSR -55^oC to +125^oC Intersil Class 14 Lead SBDIP
S Equivalent
HCTS86KMSR -55^oC to +125^oC Intersil Class 14 Lead Ceramic
S Equivalent Flatpack
HCTS86D/
Sample
+25^oC
Sample
14 Lead SBDIP
HCTS86K/
Sample
+25^oC
Sample
14 Lead Ceramic
Flatpack
HCTS86HMSR
+25^oC
Die
Die
TRUTH TABLE
INPUTS
OUTPUTS
An
Bn
Yn
L
L
L
L
H
H
H
L
H
H
H
L
NOTE: L = Logic Level Low, H = Logic level High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
Spec Number 518623
File Number 2249.2