HCS373MS Datasheet, PDF (1/10 Pages) Intersil Corporation – Radiation Hardened Octal Transparent Latch, Three-State

HCS373MS
September 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Features
Pinouts
• 3 Micron Radiation Hardened CMOS SOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm²/mg
• Single Event Upset (SEU) Immunity < 2 x 10^-9 Errors/Bit-
Day (Typ)
• Dose Rate Survivability: >1 x 10¹² RAD (Si)/s
• Dose Rate Upset >10¹⁰ RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
20 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T20
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
• Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
20 LEAD CERAMIC METAL SEAL
Description
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F20
The Intersil HCS373MS is a Radiation Hardened octal transpar-
TOP VIEW
ent three-state latch with an active-low output enable. The _OE
HCS373MS utilizes advanced CMOS/SOS technology. The out- _Q0
puts are transparent to the inputs when the Latch Enable (LE) is _D0
HIGH. When the Latch Enable (LE) goes LOW, the data is
D1
latched. The Output Enable (OE) controls the three-state outputs.
When the Output Enable (OE) is HIGH, the outputs are in the ^Q1
high impedance state. The latch operation is independent of the ^Q2
state of the Output Enable.
D2
D3
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
VCC
Q7
D7
D6
Q6
Q5
D5
D4
The HCS373MS utilizes advanced CMOS/SOS technology to _Q3
9
12
Q4
achieve high-speed operation. This device is a member of _GND
10
11
LE
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS373MS is supplied in a 20 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART NUMBER
HCS373DMSR
HCS373KMSR
HCS373D/Sample
HCS373K/Sample
HCS373HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
346
Spec Number 518845
File Number 2135.2