CDP68HC68T1 Datasheet, PDF (1/24 Pages) Intersil Corporation – CMOS Serial Real-Time Clock With RAM and Power Sense/Control

CDP68HC68T1
August 1997
CMOS Serial Real-Time Clock With
RAM and Power Sense/Control
Features
Pinouts
• SPI (Serial Peripheral Interface)
• Full Clock Features
- Seconds, Minutes, Hours (12/24, AM/PM), Day of
Week, Date, Month, Year (0-99), Automatic Leap Year
• 32 Word x 8-Bit RAM
• Seconds, Minutes, Hours Alarm
• Automatic Power Loss Detection
• Low Minimum Standby (Timekeeping) Voltage . . . 2.2V
• Selectable Crystal or 50/60Hz Line Input
• Buffered Clock Output
• Battery Input Pin that Powers Oscillator and also
Connects to V_DD Pin When Power Fails
• Three Independent Interrupt Modes
- Alarm
- Periodic
- Power-Down Sense
Description
The CDP68HC68T1 Real-Time Clock provides a
time/calendar function, a 32 byte static RAM, and a 3 wire
Serial Peripheral Interface (SPI Bus). The primary function of
the clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. The internal
oscillator can operate with a 32KHz, 1MHz, 2MHz, or 4MHz
crystal. An external clock source with a 32KHz, 1MHz,
2MHz, 4MHz, 50Hz or 60Hz frequency can be used to drive
the CDP68HC68T1. The time registers hold seconds,
minutes, and hours, while the calendar registers hold day-of-
week, date, month, and year information. The data is stored
in BCD format. In addition, 12 or 24 hour operation can be
selected. In 12 hour mode, an AM/PM indicator is provided.
The T1 has a programmable output which can provide one
of seven outputs for use elsewhere in the system.
Computer handshaking is controlled with a “wired-OR”
interrupt output. The interrupt can be programmed to provide
a signal as the result of: 1) an alarm programmed to occur at
a predetermined combination of seconds, minutes, and
hours; 2) one of 15 periodic interrupts ranging from sub-
second to once per day frequency; 3) a power fail detect.
The PSE output and the V_SYS input are used for external
power control. The CPUR output is available to reset the
processor under power-down conditions. CPUR is enabled
under software control and can also be activated via the
CDP68HC68T1’s watchdog. If enabled, the watchdog
requires a periodic toggle of the CE pin without a serial
transfer.
CDP68HC68T1 (PDIP, SBDIP, SOIC)
TOP VIEW
CLKOUT 1
CPUR 2
INT 3
SCK 4
MOSI 5
MISO 6
CE 7
V_SS 8
16 V_DD
15 XTAL OUT
14 XTAL IN
13 V_BATT
12 V_SYS
11 LINE
10 POR
9 PSE
CDP68HC68T1 (SOIC)
TOP VIEW
CLK OUT 1
CPUR 2
INT 3
NC 4
SCK 5
MOSI 6
MISO 7
CE 8
V_SS 9
PSE 10
20 VDD
19 XTAL OUT
18 XTAL IN
17 NC
16 V_BATT
15 V_SYS
14 NC
13 NC
12 LINE
11 POR
Ordering Information
TEMP.
PART NUMBER RANGE (^oC) PACKAGE
PKG.
NO.
CDP68HC68T1E
-40 to 85 16 Ld PDIP E16.3
CDP68HC68T1D
-40 to 85 16 Ld SBDIP D16.3
CDP68HC68T1M
-40 to 85 20 Ld SOIC M20.3
CDP68HC68T1M2 -40 to 85 16 Ld SOIC M16.3
CDP68HC68T1W
-40 to 85 DIE
NOTE: Pin number references throughout this specification refer to
the 16 lead PDIP/SBDIP/SOIC. See pinouts for cross reference.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 1547.3