CDP68HC68P1 Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Serial 8-Bit Input/Output Port

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Data Sheet
CDP68HC68P1
September 2003
FN1858.3
CMOS Serial 8-Bit Input/Output Port
The CDP68HC68P1 is a serially addressed 8-bit
Input/Output port that allows byte or individual bit control. It
consists of three registers, an output buffer and control logic.
Data is shifted in and out of the device via shift register that
utilizes the SPI (Serial Peripheral Interface) bus. The I/O port
data flow is controlled by the Data Direction Register and
data is stored in the Data Register that outputs or senses the
logic levels at the buffered I/O pins. All inputs, including the
serial interface are Schmitt triggered. This device also
features a compare function that compares the data register
and port pin values for 4 programmable conditions and sets
a software accessible flag if the condition is satisfied. The
user also has the option of bit-set or bit-clear when writing to
the data register.
Ordering Information
PART NUMBER
CDP68HC68P1E
CDP68HC68P1M
TEMP.
RANGE (^oC) PACKAGE
-55 to 85 16 Ld PDIP
-55 to 85 16 Ld SOIC
PKG.
NO.
E16.3
M16.15
Features
• Fully Static Operation
• Operating Voltage Range 3-6V
• Compatible with Intersil/Motorola SPI Bus
• 2 External Address Pins Tied to V_DD or V_SS to Allow Up to
4 Devices to Share the Same Chip Enable
• Versatile Bit-Set and Bit-Clear Capability
• Accepts Either SCK Clock Polarity - SCK Voltage Level is
Latched When Chip Enable Goes Active
• All Inputs are Schmitt-Trigger
• 8-Bit I/O Port - Each Bit can be Individually Programmed
as an Input or Output Via an 8-Bit Data Direction Register
• Programmable On Board Comparator
• Simultaneous Transfer of Compare Information to CPU
During Read or Write - Separate Access Not Required
Pinout
CDP68HC68P1
(PDIP, SOIC)
TOP VIEW
ID₀ 1
ID₁ 2
MISO 3
MOSI 4
SCK 5
CE 6
DO 7
V_SS 8
16 V_DD
15 D1
14 D2
13 D3
12 D4
11 D5
10 D6
9 D7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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