CDP68HC68A2 Datasheet, PDF (1/14 Pages) Intersil Corporation – CMOS Serial 10-Bit A/D Converter

CDP68HC68A2
July 1998
CMOS Serial 10-Bit A/D Converter
Features
• 10-Bit Resolution
• 8-Bit Mode for Single Data Byte Transfers
• SPI (Serial Peripheral Interface) Compatible
• Operates Ratiometrically Referencing V_DD or an
External Source
• 14µs 10-Bit Conversion Time
• 8 Multiplexed Analog Input Channels
• Independent Channel Select
• Three Modes of Operation
• On Chip Oscillator
• Low Power CMOS Circuitry
• Intrinsic Sample and Hold
• 16 Lead Dual-In-Line Plastic Package
• 20 Lead Dual-In-Line Small Outline Plastic Package
• Evaluation Board available - CDP68HC05C16BEVAL
Ordering Information
TEMP. RANGE
PART NUMBER
(^oC)
PACKAGE
PKG.
NO.
CDP68HC68A2E
-40 to 85 16 Ld PDIP E16.3
CDP68HC68A2M
-40 to 85 20 Ld SOIC M20.3
Description
The CDP68HC68A2 is a CMOS 8-bit or 10-bit successive
approximation analog to digital converter (A/D) with a
standard Serial Peripheral Interface (SPI) bus and eight mul-
tiplexed analog inputs. Voltage referencing is user selectable
to be relative to either V_DD or analog channel 0 (AI0). The
analog inputs can range between V_SS and V_DD.
The CDP68HC68A2 employs a switched capacitor,
successive approximation A/D conversion technique which
provides an inherent sample-and-hold function. An onchip
Schmitt oscillator provides the internal timing for the A/D
converter. The Schmitt input can be externally clocked or
connected to a single, external capacitor to form an RC
oscillator with a period of approximately 10-30ns per
picofarad.
Conversion times are proportional to the oscillator period. At
the maximum specified frequency of 1MHz, 10-bit
conversions take 14µs per channel. At the same frequency,
8-bit conversions consume 12µs per channel.
The versatile modes of the CDP68HC68A2 allow any
combination of the eight input channels to be enabled and
any one of the selected channels to be specified as the
“starting” channel. Conversions proceed sequentially
beginning with the starting channel. Nonselected channels
are skipped. Modes can be selected to: sequence from
channel to channel on command; sequence through
channels automatically, converting each channel one time;
or sequence repeatedly through all channels.
The results of 10-bit conversions are stored in 8-bit register
pairs (one pair per channel). The two most significant bits
are stored in the first register of each pair and the eight least
significant bits are stored in the second register of the pair.
To allow faster access, in the 8-bit mode, the results of
conversions are stored in a single register per channel.
A read-only STATUS register facilitates monitoring the
status of conversions. The STATUS register can simply be
polled or the INT pin can be enabled for interrupt driven
communications.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 1963.3