CDP1855 Datasheet, PDF (1/15 Pages) Intersil Corporation – 8-Bit Programmable Multiply/Divide Unit

March 1997
CDP1855,
CDP1855C
8-Bit Programmable
Multiply/Divide Unit
Features
• Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply
÷ or 64 32-Bit Divide
÷ • 8-Bit by 8-Bit Multiply or 16 8-Bit Divide in 5.6µs at
5V or 2.8µs at 10V
• Direct Interface to CDP1800-Series Microprocessors
• Easy Interface to Other 8-Bit Microprocessors
• Significantly Increases Throughput of Microprocessor
Used for Arithmetic Calculations
Ordering Information
PACKAGE TEMP. RANGE
5V
PDIP
-40^oC to +85^oC CDP1855CE
PKG.
10V
NO.
CDP1855E E28.6
Burn-In
SBDIP
CDP1855CEX
-
E28.6
-40^oC to +85^oC CDP1855CD CDP1855D D28.6
Burn-In
CDP1855CDX
-
D28.6
Description
The CDP1855 and CDP1855C are CMOS 8-bit multi-
ply/divide units which can be used to greatly increase the
capabilities of 8-bit microprocessors. They perform multiply
and divide operations on unsigned, binary operators. In
general, microprocessors do not contain multiply or divide
instructions and even efficiently coded multiply or divide
subroutines require considerable memory and execution
time. These multiply/divide units directly interface to the
CDP1800-series microprocessors via the N-lines and can
easily be configured to fit in either the memory or I/O space
of other 8-bit microprocessors.
The multiple/divide unit is based on a method of multiplying
by add and shift right operations and dividing by subtract and
shift left operations. The device is structured to permit cas-
cading identical units to handle operands up to 32 bits.
The CDP1855 and CDP1855C are functionally identical.
They differ in that the CDP1855 has a recommended
operating voltage range of 4V to 10.5V, and the CDP1855C,
a recommended operating voltage range of 4V to 6.5V.
The CDP1855 and CDP1855C types are supplied in a 28
lead hermetic dual-in-line ceramic package (D suffix) and in
a 28 lead dual-in-line plastic package (E suffix). The
CDP1855C is also available in chip form (H suffix).
Pinout
28 LEAD DIP
TOP VIEW
Circuit Configuration
+V
CE 1
CLEAR 2
CTL 3
C.O./O.F. 4
Y_L 5
Z_L 6
SHIFT 7
CLK 8
STB 9
RD/WE 10
RA2 11
RA1 12
RA0 13
V_SS 14
28 V_DD
27 CN0
26 CN1
25 CI
24 Y_R
23 Z_R
22 BUS 7
21 BUS 6
20 BUS 5
19 BUS 4
18 BUS 3
17 BUS 2
16 BUS 1
15 BUS 0
CLEAR
XTAL
N0
N1
N2
TPB
MRD
CDP1802
EF
BUS
CLEAR
CLK
CE
RA0
C1
RA1
CN0
RA2
CN1
STB
RD/WE
CDP1855
Y_L
Z_R
CTL
C0
Y_R
Z_L
BUS
FIGURE 1. MDU ADDRESSED AS I/O DEVICE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-47
File Number 1053.2