CDP1853C Datasheet, PDF (1/7 Pages) Intersil Corporation – High-Reliability CMOS N-Bit 1 of 8 Decoder

CDP1853C/3
March 1997
High-Reliability CMOS N-Bit 1 of 8 Decoder
Features
Description
• Provides Direct Control of Up to 7 Input and 7 Output
Devices When used with a CDP1800-Series Micropro-
cessor
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
PACKAGE TEMP. RANGE
5V
SBDIP
-55^oC to +125^oC CDP1853CD3
PKG.
10V NO.
- D16.3
The CDP1853/3 and CDP1853C/3 are high-reliability 1 of 8
decoders designed for use in general purpose microproces-
sor systems. These devices, which are functionally identical,
are specifically designed for use as gated N-bit decoders
and interface directly with the 1800-Series microprocessors
without additional components. The CDP1853/3 has a rec-
ommended operating voltage range of 4V to 10.5V, and the
CDP1853C/3 has a recommended operating voltage range
of 4V to 6.5V.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low
transition) to the trailing edge of CLOCK B (high-to-low
transition). All outputs will be low when the device is not
selected (CE = 0) and during conditions of CLOCK A and
CLOCK B as shown in Figure 2. The CDP1853/3 inputs N0,
N1, N2, CLOCK A, and CLOCK B are connected to 1800-
series microprocessor outputs N0, N1, N2, TPA, and TPB
respectively, when used to decode I/O commands as shown
in Figure 5. The CHIP ENABLE (CE) input provides the capa-
bility for multiple levels of decoding as shown in Figure 6.
The CDP1853/3 can also be used as a general purpose 1 of
8 decoder for I/O and memory system applications as shown
in Figure 4.
Pinout
16 LEAD SBDIP
TOP VIEW
CLK A 1
N0 2
N1 3
OUT 0 4
OUT 1 5
OUT 2 6
OUT 3 7
V_SS 8
16 V_DD
15 CLK B
14 N2
13 CE
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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