CDP1852 Datasheet, PDF (1/9 Pages) Intersil Corporation – Byte-Wide Input/Output Port

TM
CDP1852,
CDP1852C
March 1997
Byte-Wide Input/Output Port
Features
• Static Silicon-Gate CMOS Circuitry
• Parallel 8-Bit Data Register and Buffer
• Handshaking Via Service Request Flip-Flop
• Low Quiescent and Operating Power
• Interfaces Directly with CDP1800-Series
Microprocessors
• Single Voltage Supply
• Full Military Temperature Range (-55^oC to +125^oC)
Ordering Information
PACKAGE
PDIP
SBDIP
TEMP. RANGE
5V
10V
-40^oC to +85^oC CDP1852CE CDP1852E
-40^oC to +85^oC CDP1852CD CDP1852D
PKG.
NO.
E24.6
D24.6
Description
The CDP1852 and CDP1852C are parallel, 8-bit, mode-pro-
grammable input/output ports. They are compatible and will
interface directly with CDP1800-series microprocessors. They
are also useful as 8-bit address latches when used with the
CDP1800 multiplexed address bus and as I/O ports in general-
purpose applications.
The mode control is used to program the device as an input port
(mode = 0) or as an output port (mode = 1). The SR/SR output
can be used as a signal to indicate when data is ready to be
transferred. In the input mode, a peripheral device can strobe
data into the CDP1852, and microprocessor can read that data
by device selection. In the output mode, a microprocessor
strobes data into the CDP1852, and handshaking is established
with a peripheral device when the CDP1852 is deselected.
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request out-
put low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out ter-
minals (D00-D07). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are three-stated
and the service request output returns high (SR/SR =1).
In the output mode, the output drivers are enabled at all times.
Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit
register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the
clock are high (1), and are present at the data-out terminals
(D00-D07). The negative high-to-low transition of the clock
latches the data in the register. The SR/SR output goes high
(SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or
CS2 = 0) and returns low (SR/SR = 0) on the following trailing
edge of the clock.
Pinout
24 LEAD DIP
TOP VIEW
Typical CDP1802 Microprocessor System
CSI/CSI 1
MODE 2
DI0 3
DO0 4
DI1 5
DO1 6
DI2 7
DO2 8
DI3 9
DO3 10
CLOCK 11
V_SS 12
24 V_DD
23 SR/SR
22 DI7
21 DO7
20 DI6
19 DO6
18 DI5
17 DO5
16 DI4
15 DO4
14 CLEAR
13 CS2
ROM
ADDR BUS
TPA
MRD
CEO
RAM
ADDR BUS
TPA
CPU
CDP1802
MRD
MWR
N0 - N2 MRD
TPB
Q
SC0 SC1
INTERRUPT
I/O
CDP1852
DMA - IN DMA - OUT
EF1 - EF4
DATA
CONTROL
BIDIRECTIONAL DATA BUS
FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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File Number 1166.2