CDP1822 Datasheet, PDF (1/8 Pages) Intersil Corporation – 256-Word x 4-Bit LSI Static RAM

March 1997
CDP1822,
CDP1822C
256-Word x 4-Bit
LSI Static RAM
Features
Description
• Low Operating Current
- V_DD = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V
Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
Ordering Information
5V
CDP1822CE
10V
CDP1822E
PACKAGE
PDIP
TEMP. RANGE
-40^oC to +85^oC
PKG.
NO.
E22.4
CDP1822CEX CDP1822EX
CDP1822CD CDP1822D
Burn-In
E22.4
SBDIP -40^oC to +85^oC D22.4A
CDP1822CDX
-
Burn-In
D22.4A
The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory sys-
tems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output sys-
tems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by CS1 and/or
CS2.
The high noise immunity of the CMOS technology is pre-
served in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
Pinout
CDP1822, CDP1822C
(PDIP, SBDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
V_SS 8
DI1 ⁹
DO1 ¹⁰
DI2 ¹¹
22 V_DD
21 A4
20 R/W
19 CS1
18 O. D.
17 CS2
16 DO4
15 DI4
14 _DO3
13 _DI3
12 _DO2
OPERATIONAL MODES
INPUTS
MODE
Read
CHIP
SELECT
1
(CS₁)
0
CHIP
SELECT
2
(CS₂)
1
OUTPUT
DISABLE
(OD)
0
READ/
WRITE
(R/W)
1
OUTPUT
Read
Write
0
1
0
0 Data In
Write
0
1
1
0 High
Imped-
ance
Standby
1
X
X
X High
Imped-
ance
Standby
X
0
X
X High
Imped-
ance
Output
X
X
Disable
1
X High
Imped-
ance
NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-11
File Number 1074.2