CD4086BMS Datasheet, PDF (1/9 Pages) Intersil Corporation – CMOS Expandable 4-Wide 2-Input AND-OR-INVERT Gate

CD4086BMS
December 1992
CMOS Expandable 4-Wide 2-Input
AND-OR-INVERT Gate
Features
Pinout
• Medium Speed Operation - tPHL = 90ns; tPLH = 140ns
(Typ.) at 10V
• High Voltage Type (20V Rating)
• INHIBIT and ENABLE Inputs
• Buffered Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4086BMS contains one 4-wide 2-input AND-OR-INVERT
gate with an INHIBIT/EXP input and an ENABLE/EXP input.
For a 4-wide A-O-I function INHIBIT/EXP is tied to VSS and
ENABLE/EXP to VDD. See Figure 2 and its associated
explanation for applications where a capability greater than
4-wide is required.
The CD4076B is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H4F
CD4086BMS
TOP VIEW
A1
B2
J = INH + ENABLE +
AB + CD + EF + GH ³
NC 4
E5
F6
VSS 7
14 VDD
13 D
12 C
11 ENABLE/EXP
10 INHIBIT/EXP
9H
8G
NC = NO CONNECTION
Functional Diagram
10 INHIBIT/EXP
1
A2
B
12
C ₁₃
D
5
E6
F
8
G9
H
11 ENABLE/EXP
3
J
LOGIC 1 ≡ HIGH
LOGIC 0 ≡ LOW
VDD = 14
VSS = 7
NC = 4
J = INH + ENABLE + AB + CD + EF + GH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1055
File Number 3328