CD4078BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS 8 Input NOR/OR Gate

CD4078BMS
December 1992
CMOS 8 Input NOR/OR Gate
Features
• High Voltage Type (20V Rating)
• Medium Speed Operation
- tPHL, tPLH = 75ns (Typ.) at VDD = 10V
• Buffered Inputs and Output
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
CD4078BMS NOR/OR Gate provides the system designer with
direct implementation of the positive logic 8 input NOR and OR
functions and supplements the existing family of CMOS gates.
The CD4078BMS is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4Q
H1B
H3W
Pinout
CD4078BMS
TOP VIEW
K ** 1
A2
B3
C4
D5
NC 6
VSS 7
14 VDD
13 J *
12 H
11 G
10 F
9E
8 NC
* ^{J = A + B + C + D + E + F + G + H} ** ^{K = A + B + C + D + E + F + G + H}
NC = NO CONNECTION
Functional Diagram
2
A
3
B
4
C
5
D
9
E
F ¹⁰
11
G
12
H
1
K
13
J
J=A+B+C+D+E+F+G+H
K=A+B+C+D+E+F+G+H
6, 8 = NO CONNECTION
VDD = 14
VSS = 7
Logic Diagram
A2
B3
C4
D5
E9
F 10
13 J
1K
G 11
H 12
FIGURE 1. LOGIC DIAGRAM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1038
File Number 3326