CD4050BMS Datasheet, PDF (1/7 Pages) Intersil Corporation – CMOS Hex Buffer/Converter

CD4050BMS
December 1992
File Number 3193
CMOS Hex Buffer/Converter
The CD4050BMS is an non-inverting hex buffer and features
logic level conversion using only one supply voltage (VCC).
The input signal high level (VIH) can exceed the VCC supply
voltage when this device is used for logic level conversions.
This device is intended for use as CMOS to DTL/TTL
converters and can drive directly two DTL/TTL loads. (VCC
= 5V, VOL ≤ 0.4V, and IOL ≥ 3.3mA.
The CD4050BMS is designated as replacement for
CD4010B. Because the CD4050BMS requires only one
power supply, it is preferred over the CD4010B and should
be used in place of the CD4010B in all inverter, current
driver, or logic level conversion applications. In these appli-
cations the CD4050BMS is pin compatible with the
CD4010B, and can be substituted for this device in existing
as well as in new designs. Terminal No. 16 is not connected
internally on the CD4050BMS, therefore, connection to this
terminal is of no consequence to circuit operation. For appli-
cations not requiring high sink current or voltage conversion,
the CD4069UB Hex Inverter is recommended.
The CD4050BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP H4T
Frit Seal DIP
H1E
Ceramic Flatpack H3X
Features
• High Voltage Type (20V Rating)
• Non-Inverting Type
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• 5V, 10V and 15V Parametric Ratings
Applications
• CMOS to DTL/TTL Hex Converter
• CMOS Current “Sink” or “Source” Driver
• CMOS High-to-Low Logic Level Converter
Pinout
CD4050BMS
TOP VIEW
VCC 1
G=A 2
A3
H=B 4
B5
I=C 6
C7
VSS 8
16 NC
15 L = F
14 F
13 NC
12 K = E
11 E
10 J = D
9D
Functional Diagram
3
A
5
B
7
C
1
VCC
8
VSS
NC = 13
NC = 16
9
D
11
E
14
F
2
G=A
4
H=B
6
I=C
10
J=D
12
K=E
15
L=F
Schematic Diagram
VCC
R
IN
P
P
OUT
N
N
VSS
FIGURE 1. SCHEMATIC DIAGRAM, 1 OF 6 IDENTICAL UNITS
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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