CD40102BMS Datasheet, PDF (1/13 Pages) Intersil Corporation – CMOS 8-Stage Presettable Synchronous Down Counters

December 1992
CD40102BMS
CD40103BMS
CMOS 8-Stage Presettable
Synchronous Down Counters
Features
Description
• High Voltage Type (20V Rating)
• CD40102BMS: 2-Decade BCD Type
• CD40103BMS: 8-Bit Binary Type
• Synchronous or Asynchronous Preset
• Medium Speed Operation
- fCL = 3.6MHz (Typ) at 10V
• Cascadable
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD40102BMS and CD40103BMS consist of an 8-stage syn-
chronous down counter with a single output which is active
when the internal count is zero. The CD40102BMS is config-
ured as two cascaded 4-bit BCD counters, and the
CD40103BMS contains a single 8-bit binary counter. Each
type has control inputs for enabling or disabling the clock, for
clearing the counter to its maximum count, and for presetting
the counter either synchronously or asynchronously. All con-
trol inputs and the CARRY-OUT/ZERO-DETECT output are
active-low logic.
In normal operation, the counter is decremented by one
count on each positive transition of the CLOCK. Counting is
inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE)
inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD)
output goes low when the count reaches zero if the CI/CE
input is low, and remains low for one full clock period.
When the SYNCHRONOUS PRESET-ENABLE (SPE) input
is low, data at the JAM input is clocked into the counter on
the next positive clock transition regardless of the state of
the CI/CE input. When the ASYNCHRONOUS PRESET-
ENABLE (APE) input is low, data at the JAM inputs is asyn-
chronously forced into the counter regardless of the state of
the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 repre-
sent two 4-bit BCD words for the CD40102BMS and a single
8-bit binary word for the CD40103BMS.
Applications
• Divide-By- “N” Counters
• Programmable Times
• Interrupt Timers
• Cycle/Program Counter
When the CLEAR (CLR) input is low, the counter is asyn-
chronously cleared to its maximum count (99₁₀ for the
CD40102BMS and 255₁₀ for the CD40103BMS) regardless
of the state of any other input. The precedence relationship
between control inputs is indicated in the truth table.
If all control inputs except CI/CE are high at the time of zero
count, the counters will jump to the maximum count, giving a
counting sequence of 100 or 256 clock pulses long.
Pinout
CD40102BMS, CD40130BMS
TOP VIEW
CLOCK 1
CLEAR 2
CARRY IN/ ₃
COUNTER ENABLE
J0 4
J1 5
J2 6
J3 7
VSS 8
16 VDD
15
SYNCHRONOUS
PRESET ENABLE
14 ^{CARRY OUT/}
ZERO DETECT
13 J7
12 J6
11 J5
10 J4
9 ASYNCHRONOUS
PRESET ENABLE
This causes the CO/ZD output to go low to enable the clock
on each succeeding clock pulse.
The CD40102BMS and CD40103BMS may be cascaded
using the CI/CE input and the CO/ZD output, in either a syn-
chronous or ripple mode as shown in Figures 16 and 17.
The CD40102MS and CD40103BMS are supplied in these
16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD40102B Only
*H4W †H4X
*H1L †H1F
H6W
†CD40130B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1294
File Number 3351