CD40101BMS Datasheet, PDF (1/8 Pages) Intersil Corporation – CMOS 9-Bit Parity Generator/Checker

CD40101BMS
December 1992
CMOS 9-Bit Parity Generator/Checker
Features
Pinout
• High Voltage Type (20V Rating)
• 100% Tested for Quiescent Current at 20V
CD40101BMS
TOP VIEW
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25^oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
D1 1
D2 2
D3 3
D4 4
D9 5
ODD OUT 6
VSS 7
14 VDD
13 D8
12 D7
11 D6
10 D5
9 EVEN OUT
8 INHIBIT
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Description
The CD40101BMS is a 9-bit (8 data bits plus 1 parity bit)
parity generator/checker. It may be used to detect errors in
data transmission or data retrieval. Odd and even outputs
facilitate odd or even parity generation and checking.
Functional Diagram
INHIBIT
8
When used as a parity generator, a parity bit is supplied
along with the data to generate an even or odd parity output.
D1 1
When used as a parity checker, the received data bits and
parity bits are compared for correct parity. The even or odd
outputs are used to indicate an error in the received data.
D2 2
Word length capability is expandable by cascading. The
CD40101BMS is also provided with an inhibit control. If the
inhibit control is set at logical “1”, the even and odd outputs
go to a logical “0”.
D3 3
D4 4
The CD40101BMS is supplied in these 14 lead outline
packages:
D5 10
DECODE
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H3W
D6 11
D7 12
VDD = 14
VSS = 7
EVEN
OUTPUT
9
ODD
OUTPUT
6
D8 13
D9 5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1286
File Number 3350