CA3242 Datasheet, PDF (1/1 Pages) Intersil Corporation – Quad-Gated Inverting Power Driver For Interfacing Low-Level Logic to High Current Load

CA3242
August 1998
Quad-Gated Inverting Power Driver For
Interfacing Low-Level Logic to High Current Load
Features
Description
• Driven Outputs Capable of Switching 600mA Load
Currents Without Spurious Changes in Output State
• Inputs Compatible with TTL or 5V CMOS Logic
• Suitable for Resistive or Inductive Loads
• Output Overload Protection
• Power-Frame Construction for Good Heat Dissipation
Applications
• Relays
• Solenoids
• AC and DC Motors
• Heaters
• Incandescent Displays
• Vacuum Fluorescent Displays
Ordering Information
The CA3242 quad-gated inverting power driver contains four
gate switches for interfacing low-level logic to inductive and
resistive loads such as: relays, solenoids, AC and DC
motors, heaters, incandescent displays, and vacuum fluo-
rescent displays.
Output overload protection is provided when the load current
(approximately 1.2A) causes the output V_CE(sat) to rise
above 1.3V. A built-in time delay, nominally 25µs, is provided
during output turn-on as output drops from V_DD to V_SAT. That
output will be shut down by its protection network without
affecting the other outputs. The corresponding Input or
Enable must be toggled to reset the output protection circuit.
Steering diodes in the outputs in conjunction with external
zener diodes protect the IC against voltage transients due to
switching inductive loads.
To allow for maximum heat transfer from the chip, the four
center leads are directly connected to the die mounting pad.
In free air, junction-to-air thermal resistance (R_θJA) is 60^oC/W
(typical). This coefficient can be lowered by suitable design
of the PC board to which the CA3242 is soldered.
PART NUMBER
CA3242E
TEMPERATURE
RANGE
-40^oC to +105^oC
PACKAGE
16 Lead Plastic DIP
Pinout
Block Diagram
CA3242 (PDIP)
TOP VIEW
P
OUT A 1
16 IN A
IN D 9
CLAMP 2
15 IN B
IN C 10
P
OUT B 3
14 ENABLE
GND 4
13 GND
VCC ¹¹
GND 5
OUT C 6
CLAMP 7
12 GND
11 _VCC
10 INC
GND 12
GND 13
OUT D 8
9 IND
ENABLE 14
P
IN B ¹⁵
P
IN A ¹⁶
8 OUT D
7 CLAMP
6 OUT C
5 GND
4 GND
3 _{OUT B}
2 CLAMP
1 _{OUT A}
TRUTH TABLE
ENABLE IN OUT
H
H
L
H
L
H
L
X
H
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
2-3
File Number 1561.2