AN1673.0 Datasheet, PDF (1/4 Pages) Intersil Corporation – Application Circuit to Generate Plus

Application Note 1673
Authors: Don LaFontaine, Dan Goodhew
Application Circuit to Generate Plus and Minus
Supplies Using the ISL97701 Boost Regulator
Introduction
This application note will discuss a method to combine the
operation of a boost regulator and a negative voltage
converter. The circuit described will generate both a positive
and a negative supply from a single low voltage supply. The
circuit in Figure 5 shows the standard ISL97701 application
circuit for a +20V supply along with two ISL28107 op amps,
two diodes and two capacitors to generate a well regulated
-20V supply.
Understanding the Boost Topology
Before we add the additional circuitry to generate the negative
supply, it is important to understand how the boost convertor
produces an output voltage that is always greater than the
input voltage. In order to do this, we analyze the boost circuits
in Figure 1 and the current waveforms in Figure 2. For this
analysis, we account for all the losses in the charging and
discharging loops in our equations. This should help to give a
complete understanding of the circuit.
However, the ISL97701’s output voltage is not dependent upon
any losses in the circuit. This is because all the losses are
inside the circuit’s feedback loop of the ISL97701, and are
automatically accounted for. The output voltage is defined
from the feedback resistor network shown in Figure 5 and
calculated in Equation 1, where V_refFB is the internal reference
voltage of the ISL97701.
V_OUT = V_refFB • (R₁ + R₂) ⁄ R₂
V_OUT = 1.15V • (R₁ + R₂) ⁄ R₂
(EQ. 1)
Positive Supply
Figure 1A shows the basic boost converter circuit. During one
switching cycle, the transistor Q₁ turns on and turns off. During
the time Q₁ is on, the inductor L₁ is placed in series with the
V_IN supply through the ISL97701’s integrated boost FET (Q₁).
The diode D₁ is reversed biased and the circuit reduces to that
shown in Figure 1B. The voltage across the boost inductor (L₁)
is equal to V_IN - (V_DS + I_L1 x R_L1) and the current ramps up
linearly in inductor L₁ to a peak value at time DT. The peak
inductor current (Δ I_L1(on)) is calculated in Equation 3 and
shown graphically in Figure 1B. Any load requirements during
this phase are supplied by the output capacitor C₁.
DT
∫ ^VL
=
L
×
d_----i_--L-
dt
⇒
i_Lpk
=
-^V---^L-
L
dt
(EQ. 2)
T0
ΔI _{L 1 ( o n )}
=
V_{----I--N-----–----}(_---V_{---D----S----+-----}I_--L---1-----×_-----R_{----L---1----}) _{× DT}
L
(EQ. 3)
When Q₁ turns off, since the current in an inductor cannot
change instantaneously, the voltage in L₁ reverses and the
circuit becomes that shown in Figure 1C. Now the no-dot end
of L₁ is positive with respect to the dot end and D₁ becomes
forward biased. Since the dot end is at V_IN, L₁ delivers its
stored energy to C₁ and charges it up to a higher voltage than
V_IN. This energy supplies the load current and replenishes the
charge drained away from C₁. During this time, energy is also
supplied to the load from V_IN. The voltage applied to the dot
end of the inductor is (V_IN - I_L1 x R_L1). The voltage applied to
the no-dot end of L₁ is now the output voltage, V_O, plus the
diode forward voltage V_D. The voltage across the inductor
during the off-state is ((V_O + V_{D1 +} I_L1 x R_L1) - V_IN). The inductor
current during the off-time of the switch (T-DT) is calculated in
Equation 4 and shown graphically in Figure 1C.
ΔI_{L 1 ( o f f )}
=
(_---V_{---O-----+-----}V_{----D----1----+-----}I_--L---1----×_-----R_{----L---1----})_{---–-----}V_---I--N--
L
×
(T
–
DT
)
(EQ. 4)
In steady-state conditions, the current increases during the
on-time of the switch and decreases during the off-time of the
switch, reference Figure 2. Both on-time and off-time currents
are equal to prevent the inductor core from saturating. Setting
both currents equal to each other and solving for V_O results in
the continuous conduction mode boost voltage shown in
Equation 5.
V_O
=
-^V---^I--^N-----–----^I--^L----^×-----^R----^L-
1–D
–
V_D
1
–
V_DS
×
-----^D-------
1–D
(EQ. 5)
R_L1
V_IN
I_L1
+
-
L₁
Q₁
D₁
V_O
I_o
C₁ R_L
FIGURE 1A.
R_L1
L₁
Δ I_L1(on)= (V_IN-(V_DS + I_L1xR_L1))DT
L
V_IN ^IL1
+
-
Q₁
IQ₁
V_DS
I_Q1
0T
DT
FIGURE 1B.
R_L1 L₁
V_IN IL1
+
-
D₁
I_D
Δ I_L1(off) = (V_O+V_D+I_L1xR_L)-V_IN(T-DT)
V_{O ID}
L
C₁ R_L
DT
T
FIGURE 1C.
FIGURE 1. BASIC BOOST TOPOLOGY
November 18, 2011
1
AN1673.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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