ACTS373MS Datasheet, PDF (1/10 Pages) Intersil Corporation – Radiation Hardened Octal Transparent Latch, Three-State

ACTS373MS
April 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10^-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm²/mg
• Dose Rate Upset >10¹¹ RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2V Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACTS373MS is a radiation hardened octal transpar-
ent latch with three-state outputs. The outputs are transparent to
the inputs when the latch enable (LE) is high. When the LE goes
low, the data is latched. When the Output Enable (OE) is high,
the outputs are in the high impedance state. The latch operation
is independent of the state of the output enable.
The ACTS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Ordering Information
PART NUMBER
ACTS373DMSR
ACTS373KMSR
ACTS373D/Sample
ACTS373K/Sample
ACTS373HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Truth Table
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
I
L
L
L
h
H
H
X
X
Z
NOTE:
L = Low Voltage Level
H = High Voltage Level
X = Don’t Care
Z = High Impedance State
I = Low voltage level one set-up time prior to the high to low latch enable transition
h = High voltage level one set-up time prior to the high to low latch enable transition
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
LATCH
DQ
COMMON
LE
CONTROLS
LE
(11)
OE
(1)
OE
Q
(2, 5, 6, 9, 12,
15, 16, 19)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518800
File Number 4000