ACTS08MS Datasheet, PDF (1/8 Pages) Intersil Corporation – Radiation Hardened Quad 2-Input AND Gate

ACTS08MS
April 1995
Radiation Hardened
Quad 2-Input AND Gate
Features
Pinouts
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10^-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm²/mg
• Dose Rate Upset >10¹¹ RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55^oC to +125^oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current ≤1µA at VOL, VOH
Description
The Intersil ACTS08MS is a radiation hardened quad 2-Input
AND Gate. A high on both inputs forces the output to a high
logic level.
The ACTS08MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of a
radiation hardened, high-speed, CMOS/SOS Logic Family.
14 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T14, LEAD FINISH C
TOP VIEW
A1 1
B1 2
Y1 3
A2 4
B2 5
Y2 6
GND 7
14 VCC
13 B4
12 A4
11 Y4
10 B3
9 A3
8 Y3
14 LEAD CERAMIC FLAT PACK
MIL-STD-1835 DESIGNATOR CDFP3-F14, LEAD FINISH C
TOP VIEW
A1
B1
Y1
A2
B2
Y2
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
B4
A4
Y4
B3
A3
Y3
Ordering Information
PART NUMBER
ACTS08DMSR
ACTS08KMSR
ACTS08D/Sample
ACTS08K/Sample
ACTS08HMSR
TEMPERATURE RANGE
-55^oC to +125^oC
-55^oC to +125^oC
+25^oC
+25^oC
+25^oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
Truth Table
INPUTS
OUTPUT
An
Bn
Yn
L
L
L
L
H
L
H
L
L
H
H
H
NOTE: L = Logic Level Low, H = Logic Level High
Functional Diagram
(1, 4, 9, 12)
An
(2, 5, 10, 13)
Bn
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
(3, 6, 8, 11)
Yn
Spec Number 518851
File Number 3994