J108 Datasheet, PDF (1/1 Pages) NXP Semiconductors – N-channel silicon junction FETs

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B-49
J108, J109
N-Channel Silicon Junction Field-Effect Transistor
Absolute maximum ratings at T_A = 25¡C
Reverse Gate Source & Reverse Gate Drain Voltage
Continuous Forward Gate Current
Continuous Device Power Dissipation
Power Derating
– 25 V
50 mA
360 mW
3.27 mW/°C
At 25°C free air temperature:
Static Electrical Characteristics
Gate Source Breakdown Voltage
Gate Reverse Current
Gate Source Cutoff Voltage
Drain Saturation Current (Pulsed)
Drain Cutoff Current
Dynamic Electrical Characteristics
Drain Source ON Resistance
Drain Gate Capacitance
Source Gate Capacitance
Drain Gate + Source Gate Capacitance
Switching Characteristics
Turn ON Delay Time
Rise Time
Turn OFF Delay Time
Fall Time
V_(BR)GSS
I_GSS
V_GS(OFF)
I_DSS
I_D(OFF)
J108
J109
Min Max Min Max Unit
– 25
– 25
V
–3
– 3 nA
– 3 – 10 – 2 – 6 V
80
40
mA
3
3 nA
r_ds(on)
C_gd
C_gs
C_gd + C_gs
td_(on)
t_r
td_(off)
t_f
8
15
15
85
Typ
3
1
4
18
12 Ω
15 pF
15 pF
85 pF
Typ
3
ns
1
ns
4
ns
18
ns
Process NJ450
Test Conditions
I_G = – 1 µA, V_DS = ØV
V_GS = – 15V, V_DS = ØV
V_DS = 5V, I_D = 1 µA
V_DS = 15V, V_GS = ØV
V_DS = 5V, V_GS = – 10V
V_GS = Ø, V_DS < = 0.1V
V_DS = ØV, V_GS = – 10V
V_DS = ØV, V_GS = – 10V
V_DS = V_GS = ØV
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
V_DD
V_GS(OFF)
R_L
J108 J109
1.5
1.5
V
– 12
–7
V
150
150
Ω
TOÐ226AA Package
Dimensions in Inches (mm)
Pin Configuration
1 Drain, 2 Source, 3 Gate
www.interfet.com
Surface Mount
SMPJ108, SMPJ109
1000 N. Shiloh Road, Garland, TX 75042
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